Reduced capacitance scaled HBT using a separate base post layer

Details Reduced capacitance scaled HBT using a separate base post layer Reduced capacitance scaled HBT using a separate base post layer

2000-09-19

2003-05-20

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Bipolar transistor

C438S312000, C438S320000

Reexamination Certificate

active

06566693

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to heterojunction bipolar transistors (HBTs), integrated circuits utilizing HBTs (HBT-ICs) and methods for their fabrication.
BACKGROUND OF THE INVENTION
High-speed, complex circuitry is essential to many electronic and communications applications, including fiber optical communications, frequency synthesizers, and analog-digital conversion. Heterojunction bipolar transistors (HBTs) are preferred technology for achieving the necessary levels of both complexity and speed required by these applications.
Presently, high-speed InP HBTs are manufactured using I-line optical lithography to define as small a base-collector area on the HBT as possible. [M. Sokolich et al., GaAs IC Symposium Technical Digest, pp. 117-120, 1998]. Using this process, a 52.9 GHz static divider has been developed. In this method, the base and collector posts are patterned after the mesa has been completely etched. The height of the mesa requires that a certain photoresist thickness be used to cover the mesa. The thickness requirement limits the minimum dimensions that can be resolved by the optical lithography equipment. As a result. the base post is necessarily larger than if it were defined earlier in the process, which accordingly places a minimum limit on the base-collector area and corresponding capacitance of the HBT.
Approaches to further improving the speed of present HBTs have been reported. [Gutierrez-Aitken, A., et al., IEDM Tech. Digest, 1999; Lee, Q., et al., IEEE GaAs IC Symposium Tech. Dig., pp. 87-90, 1999]. One process for preparing faster HBTs utilizes patterned substrates and e-beam lithography. [Lee, Q., et al., IEEE GaAs IC Symposium Tech. Dig., pp. 87-90, 1999]. This process has advantages for being able to define very small features; however, it is not adaptable to manufacturing.
Yet another process relies on severe undercutting of the base metal to define a small base-collector area. [Gutierrez-Aitken, A., et al., IEDM Tech. Digest. 1999] Using this process, a 69 GHz divider was prepared. However, this process would also seem to have manufacturing and reliability concerns.
SUMMARY OF THE INVENTION
The present invention provides high-speed HBTs and a process for their fabrication that is adaptable to manufacturing and provides for faster circuit speeds than previous processes. The fabrication process of the present invention. separates the definition of the base and collector posts while maintaining the number of mask levels. Unlike the current manufacturing process referred to above and described herein, the process of the present invention allows the base post to be patterned earlier in the process prior to etching of the base. This is important because thinner photoresist can thus be used to pattern the base post. As a result, the base post is patterned on a more planar surface, thereby reducing the minimum resolvable feature size below (600 nm)
2
. The smaller base post allows reduction of the base metal contact area and the base-collector capacitance, which directly affects the speed of the resulting device.


REFERENCES:
patent: 5729033 (1998-03-01), Hafazi
patent: 5994194 (1999-11-01), Lammert
M. Sokolich et al.., “A Low Power 52.9 GHz Static Divider Implemented in a Manufacturable 180 GHz AIInAs/InGaAs HBT IC Technology”, GaAs IC Symposium Technical Digest, pp. 117-120, 1998.
A. Gutierrez-Aitken et al., “69 GHz Frequency Divider with a Cantilevered Base InP DHBT”, IEDM Technical Digest, 1999.
Sokolich, M., et al. “A low power 52.9 GHz static divider implemented in a manufacturable 180 GHz AllnAs HBT IC technology” Gallium Arsenide Integrated Circuit (GAAS IC) Symposium, 1998, Technical Digest 1998, NY, USA, IEEE, US Nov. 1, 1998, pp. 117-120, XP010309899.
Park, S. H., et al. “Submicron Self-Aligned HBT's by Selective Emitter Regrowth” IEEE Electron Device Letters, IEEE Inc. New York, US, vol. 19, No. 4, Apr. 1, 1998, pp. 118-120, XP000738793.
Lester, T., et al. “A Manufactura Process for HBT Circuits” Gallium Arsenide and Related Compounds, Freiburg, Aug. 29-Sep. 2, 1993, Proceedings of the International Symposium on Gallium Arsenide and Related Compounds, vol. SYMP 20, pp. 449-454, XP000478977.

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