Reduced capacitance resistors

Details Reduced capacitance resistors Reduced capacitance resistors

2007-07-10

2007-07-10

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S536000

Reexamination Certificate

active

11005765

ABSTRACT:
A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.

REFERENCES:
patent: 4710791 (1987-12-01), Shirato et al.
patent: 5994759 (1999-11-01), Darmawan et al.
patent: 6320241 (2001-11-01), Okamoto

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