Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant
Patent
1998-10-08
1999-10-05
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
With specified dopant
438528, 257647, H01L 2436
Patent
active
059629142
ABSTRACT:
A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.
REFERENCES:
patent: 4098618 (1978-07-01), Crowder et al.
patent: 4551910 (1985-11-01), Patterson
patent: 4578128 (1986-03-01), Mundt et al.
patent: 4682407 (1987-07-01), Wilson et al.
patent: 4707721 (1987-11-01), Ang et al.
patent: 4729009 (1988-03-01), Ang
patent: 4743566 (1988-05-01), Bastiaens et al.
patent: 4774197 (1988-09-01), Haddad et al.
patent: 4776925 (1988-10-01), Fossum et al.
patent: 4808261 (1989-02-01), Ghidini et al.
patent: 4851257 (1989-07-01), Young et al.
patent: 4866002 (1989-09-01), Shizukuishi et al.
patent: 4897365 (1990-01-01), Baldi et al.
patent: 4922319 (1990-05-01), Fukushima
patent: 5043780 (1991-08-01), Fazan et al.
patent: 5066995 (1991-11-01), Young et al.
patent: 5082797 (1992-01-01), Chan et al.
patent: 5102832 (1992-04-01), Tuttle
patent: 5138411 (1992-08-01), Sandhu
patent: 5141882 (1992-08-01), Komori et al.
patent: 5158463 (1992-10-01), Kim et al.
patent: 5172200 (1992-12-01), Muragishi et al.
patent: 5191509 (1993-03-01), Wen
patent: 5208176 (1993-05-01), Ahmad et al.
patent: 5250456 (1993-10-01), Bryant
patent: 5254489 (1993-10-01), Nakata
patent: 5286992 (1994-02-01), Ahrens et al.
patent: 5308787 (1994-05-01), Hong et al.
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5330920 (1994-07-01), Soleimani et al.
patent: 5330935 (1994-07-01), Dobuzinsky et al.
patent: 5340764 (1994-08-01), Larsen et al.
patent: 5358894 (1994-10-01), Fazan et al.
patent: 5391907 (1995-02-01), Jang
patent: 5432114 (1995-07-01), O
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5502009 (1996-03-01), Lin
patent: 5576226 (1996-11-01), Hwang
patent: 5576266 (1996-11-01), Flosenzier et al.
patent: 5576570 (1996-11-01), Ohsawa et al.
patent: 5786256 (1998-07-01), Gardner et al.
patent: 5789305 (1998-08-01), Peidous
patent: 5872376 (1999-02-01), Gardner et al.
patent: 5882993 (1999-03-01), Gardner et al.
Wolfe, S., "Silicon Processing For The VLSI Era," vol. 3: The Submicron MOSFET, Lattice Press, CA, 1985, pp. 495-496.
Wolfe, et al., "Silicon Processing For The VLSI Era," vol. 1: Process Technology, Lattice Press, CA, 1986, pp. 429-446.
Wolf, "Silicon Processing for the VLSI Era, vol. 1, Process Technology,", pp. 198-218.
Molle, P. et al., "Nitrogen Implantation for Local Oxidation of Silicon," Nuclear Instruments & Methods in Physics Research, Section -B: Bean Interactions with Materials and Atoms, vol. B55, No. 1/04, Apr. 2, 1991, pp. 860-865.
Schott, K. et al., "Blocking of Silicon Oxidation by Low-Dose Nitrogen Implantation," Applied Physics A. Solids and Surfaces, vol. A45, No. 1, Jan. 1, 1988, pp. 73-76.
Patent Abstracts of Japan, Publication No. 01183844; Publication Date: Jul. 21, 1989; Application Date: Jan. 19, 1988; Application No.: 63008901.
Doyle, B. et al., "Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing," IEEE Electron Device Letters, vol. 16, No. 7, Jul. 1995, pp. 301-302.
Philipossian, A. et al., "Kinetics of Oxide growth During Reoxidation of Lightly Nitrided Oxides," J. Electrochem. Soc. V. 139, No. 9, Sep. 1992, pp. L82-3.
Ahn, J. et al., "High Quality Ultrathin gate Dielectrics Formation by Thermal Oxidation of Si in N20," J. Electrochem. Soc. V. 139, No. 9, Sep. 1991, pp. L39-41.
Kuroi, et al "Novel NICE Structure For High Reliability and High Performance 0.25 micron Dual Gate CMOS", IEDM, pp. 325-328.
Naito et al., "Effect of Bottom Oxide on the Integrity of Interpolysilicon Ultrathin ONO Films," Journal of the Electrochemical Society, vol. 137, No. 2, Feb. 1, 1990, pp. 635-638.
Abbas et al., "Improvement of the Gate-Region Integrity in FET Devices," IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972, pp. 3348-3350.
Cheung, "Plasma Immersion Ion Implantation for ULSI Processing," Trends & Applications, 1991, pp. 811-820.
Wolfe et al., "Silicon Processing for the VLSI Era, vol. 1, Process Technology," p. 321.
Chang Kuang-Yeh
Gardner Mark I.
Hause Fred N.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Hardy David B.
Kowert Robert C.
LandOfFree
Reduced bird's beak field oxidation process using nitrogen impla does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduced bird's beak field oxidation process using nitrogen impla, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced bird's beak field oxidation process using nitrogen impla will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1174697