Reduced beta vertical transistors and method of fabrication

Details Reduced beta vertical transistors and method of fabrication Reduced beta vertical transistors and method of fabrication

1978-01-18

1986-06-17

Larkins, William D.

Metal treatment

Stock

Ferrous

357 44, 357 89, 148175, 148186, H01L 2704

Patent

active

045959439

ABSTRACT:
The current gain, beta, of a vertical transistor having an emitter formed in an epitaxial base on a substrate collector is reduced by forming a high impurity region of the conductivity type of the base at the base-collector boundary to increase the base width greater than the vertical distance between the emitter and collector. A plurality of vertical transistors having identical emitters and a common collector may be simultaneously fabricated with different current gains by individually selecting the horizontal dimensions of the buried high impurity regions.

REFERENCES:
patent: 3383607 (1968-05-01), Avins
patent: 3878551 (1975-04-01), Callahan, Jr.
patent: 3946425 (1976-03-01), Shoji et al.
Lin, Integrated Electronics, (Holden-Day, San Francisco, 1967), pp. 270-271.
Lehning, IEEE J. of Solid State Circuits, vol. SC9, Oct. 1974, p. 228.
Berger et al., IBM Tech. Discl. Bull., vol. 15, No. 5, Oct. 1972, p. 1625.

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