Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-01-16
2004-03-23
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S244000, C438S253000, C438S387000
Reexamination Certificate
active
06709945
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor processing, and more particularly to a method for forming a contact and a container capacitor for a semiconductor device such as a dynamic random access memory.
BACKGROUND OF THE INVENTION
During the manufacture of a semiconductor device such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, and logic devices, several structures are commonly formed. For example, contact openings to a conductive layer such as doped monocrystalline silicon wafer, a polycrystalline silicon (polysilicon) layer, or a metal feature through a dielectric layer such as tetraethyl orthosilicate (TEOS) and/or borophosphosilicate glass (BPSG) can be formed. Further, openings are commonly formed within a dielectric layer as an early step in the formation of a container capacitor in a memory device.
FIGS. 1-6
depict a conventional process used during the formation of a semiconductor memory device such as a DRAM to form storage capacitors and digit line contacts.
FIG. 1
depicts a semiconductor wafer substrate assembly comprising a semiconductor wafer
10
, field oxide
12
, doped wafer areas
13
, transistor control gates typically comprising a polysilicon gate
14
A and silicide
14
B, and surrounding dielectric typically comprising gate oxide
16
A, nitride spacers
16
B, and capping layer
16
C, for example TEOS.
FIG. 1
further depicts polysilicon contact pads including pads
18
to which container capacitors will be electrically coupled and pads
20
which will form a portion of a digit line contact to the wafer
10
. The pads are separated by a dielectric layer
22
, for example BPSG. Also depicted is a second layer of dielectric
24
which can be one or more layers of TEOS and/or BPSG. A layer of photoresist
26
defines openings
28
which overlie pads
18
to which the container capacitors will be electrically coupled. The structure of
FIG. 1
is exposed to a vertical anisotropic etch which removes the dielectric layer
24
selective to the polysilicon contact pads
18
.
FIG. 2
depicts openings
30
which result from the etch of the
FIG. 1
structure. The etch exposes pads
18
, which in turn contact doped regions
13
. Pads
18
, therefore, decrease the amount of oxide which the etch of the
FIG. 1
structure must remove. Without pads
18
, the etch would be required to remove the additional thickness of oxide layer
22
to expose doped regions
13
.
After forming the openings, a blanket layer of hemispherical silicon grain (HSG)
32
is formed over exposed surfaces including pads
18
. Subsequently, the openings are filled with a sacrificial protective material such as photoresist (not depicted) and the HSG and a portion of dielectric
24
are etched, for example using chemical mechanical polishing (CMP). This removes the HSG from the horizontal surface of dielectric
24
. Any protective material remaining within opening
30
is removed.
Next, blanket layers of cell nitride
34
and top plate polysilicon
36
are formed over the surface of the assembly as depicted in
FIG. 3. A
patterned photoresist layer
38
is provided which defines the storage nodes and capacitor top plate. After the etch, the photoresist
38
is removed.
As depicted in
FIG. 4
another dielectric layer
40
such as BPSG is deposited and planarized and a patterned photoresist
42
is formed over dielectric
40
. Opening
44
within the photoresist layer overlies the digit line contact pad
20
. A vertical anisotropic etch is performed which etches through dielectric layers
40
and
24
to provide a contact opening
50
and to expose the digit line contact pad
20
as depicted in FIG.
5
. The etch exposes pad
20
, which in turn contacts doped region
13
. Pad
20
, therefore, decreases the amount of oxide which the etch of the
FIG. 4
structure must remove. Without pad
22
, the etch would be required to remove the additional thickness of oxide layer
22
to expose doped region
13
. Finally, as depicted in
FIG. 6
, a conductive plug
60
typically comprising tungsten is formed within opening
50
and a metal digit line runner
62
, typically aluminum, is formed over dielectric layer
40
to electrically contact the plug
60
to provide a digit line.
One problem with a process such as that described above is that the etch of the digit line contact opening
50
to expose the digit line contact pad
20
requires etching through a very thick series of dielectric layers. With current processes the ratio of the contact opening height to the width (i.e. the “aspect ratio”) can be 10:1 or greater. For example, layer
24
depicted in
FIG. 4
can have a thickness of 14,000 angstroms (Å) or more, and layer
40
can have a thickness of 4,000 Å for a total of 18,000 Å of dielectric to etch through to form a contact about 1,150 Å wide for an aspect ratio of about 15:1. As the aspect ratio of openings increases the opening becomes increasingly difficult to form reliably. Contact locations in a periphery of a semiconductor device (see
174
in
FIG. 17
, for example) often do not have pads
18
,
20
which further increases the aspect ratio. Problems forming high aspect ratio contacts include difficulty in etching the bottom portion of the dielectric layer, in maintaining the proper diameter of toward the top of the opening, and in filling the contact opening with conductive material subsequent to its formation.
A method for forming a contact opening which reduces or eliminates the problems described above would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method that reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting from contact etches and fills requiring a high aspect ratio. In accordance with one embodiment of the invention a portion of a digit line contact opening is etched to expose a digit line contact pad, then the opening is filled with conductive material to form a digit line contact plug to the pad. A storage capacitor is subsequently formed and the remainder of the digit line plug and digit line runner are formed. This process decreases the aspect ratio of the contact openings which must be formed, and may provide increased capacitance of the storage capacitor by allowing an increased height of the capacitor as will be described in detail below.
Other advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
REFERENCES:
patent: 4656732 (1987-04-01), Teng et al.
patent: 5144579 (1992-09-01), Okabe et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5401681 (1995-03-01), Dennison
patent: 5834845 (1998-11-01), Stolmeijer
patent: 5843830 (1998-12-01), Graettinger et al.
patent: 5844771 (1998-12-01), Graettinger et al.
patent: 5869861 (1999-02-01), Chen
patent: 5956594 (1999-09-01), Yang et al.
patent: 5989952 (1999-11-01), Jen et al.
patent: 6251726 (2000-01-01), Huang
patent: 6046093 (2000-04-01), DeBoer et al.
patent: 6100137 (2000-08-01), Chen et al.
patent: 6127260 (2000-10-01), Huang
patent: 6134137 (2000-10-01), Kurth et al.
patent: 6140172 (2000-10-01), Parekh
patent: 6168984 (2001-01-01), Yoo et al.
patent: 6187624 (2001-02-01), Huang
patent: 6200855 (2001-03-01), Lee
patent: 6221711 (2001-04-01), Roberts et al.
patent: 6300191 (2001-10-01), Yu et al.
patent: 6507064 (2003-01-01), Tang et al.
Loke Steven
Martin Kevin D.
Vu Quang
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