Reduced area gate array cell design based on shifted placement o

Details Reduced area gate array cell design based on shifted placement o Reduced area gate array cell design based on shifted placement o

1997-08-21

1999-07-13

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257206, H01L 2170

Patent

active

059230606

ABSTRACT:
A gate array basic cell and circuit layout architecture for efficiently routing power supply traces. A basic cell has one or more transistors PMOS and one or more NMOS formed by diffusion regions and gate regions. A portion of the diffusion region extends outward to a point past the end of the gate region. Basic cells are arranged in rows with each basic cell having its p-type diffusion region extending in a direction opposite the n-type diffusion region. Basic cells are arranged in rows. Power supply traces are placed between rows, across the extended diffusion regions. Adjacent rows are shifted with respect to each other. A power supply trace is shared by adjacent rows of basic cells such that a connection can be made between the power supply trace and the extended diffusion regions without additional routing.

REFERENCES:
patent: 4745084 (1988-05-01), Rowson et al.
patent: 4928160 (1990-05-01), Crafts
patent: 5384472 (1995-01-01), Yin
patent: 5701021 (1997-12-01), Yin

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