Reduced area floating point processor control logic utilizing a

Details Reduced area floating point processor control logic utilizing a Reduced area floating point processor control logic utilizing a

1995-05-16

1997-11-11

Swann, Tod R.

395563, 395598, G06F 9302

Patent

active

056873409

ABSTRACT:
A control logic unit outputs a group of encoded control signals that have less redundancy than the FPU signals needed to control a floating point processor, thus requiring fewer signal lines using less area. Decoders electrically connected between the control logic unit and the floating point processor decode the control signals to provide the FPU signals. If the number of control signals is one less than the number of FPU signals, a priority encoder is used as the decoder, unless the FPU signals include a power savings signal. Otherwise a custom decoder is used. The most active signal of the group of FPU signals is selected as the signal to be eliminated when a priority encoder is used.

REFERENCES:
patent: 4229801 (1980-10-01), Whipple
patent: 4866652 (1989-09-01), Chu et al.
patent: 4887084 (1989-12-01), Yamaguchi
patent: 5070475 (1991-12-01), Normoyle et al.
patent: 5095460 (1992-03-01), Rodeheffer
patent: 5265258 (1993-11-01), Fiene et al.
patent: 5339266 (1994-08-01), Hinds et al.
patent: 5392437 (1995-02-01), Matter et al.
patent: 5394558 (1995-02-01), Arakawa et al.
patent: 5619664 (1997-04-01), Glew

Affiliated with

Also associated with

Rating

Reduced area floating point processor control logic utilizing a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced area floating point processor control logic utilizing a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced area floating point processor control logic utilizing a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1236540