Reduce width, differentially doped vertical JFET device

Details Reduce width, differentially doped vertical JFET device Reduce width, differentially doped vertical JFET device

1997-05-13

1999-08-31

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257263, 257270, 257272, 257287, H01L 2900

Patent

active

059456990

ABSTRACT:
A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the well in which the JFET is formed, and is surrounded by the JFET channel region which has a generally annular shape. The pinch-off voltage of the annular vertical JFET channel is established by its cross-sectional thickness and doping profile. This reduced thickness, annular-shaped, vertical JFET channel provides a limited current flow path that can be very precisely tailored to restrict current flow to what is essentially a leakage current path, and thereby provide a very high load impedance.

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"Session VI: Digital Circuit Techniques--MOS Buried Load Logic" by Yoshio Sakai et al; 1980 IEEE International Solid-State Circuits Conference, pp. 56-57.

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