Reduce instruction set microprocessor

Details Reduce instruction set microprocessor Reduce instruction set microprocessor

1992-08-10

1993-03-09

Harrell, Robert B.

Boots, shoes, and leggings

364DIG2, 364DIG1, 3649256, 3649235, 36423223, G06F 922

Patent

active

051932067

ABSTRACT:
A LOW RISC (reduced instruction set computer) III microprocessor reduces the number of branches taken during execution of logic, functional, and symbolic programs to increase the efficiency and effectiveness of pipelined execution memory interleave, and reduces the complexity of RISC architectures. The LOW RISC III is a 40-bit, 4-stage pipelined processor which is pipelined with each stage operating synchronously in parallel. Pipeline breaks are reduced by moving partial unification and trail checking into hardware, and eliminating many short branches by conditional execution of the various instructions.

REFERENCES:
patent: 4847755 (1989-07-01), Morrison et al.
Jonathan Wayne Mills, "A Pipelined Architecture for Logic Programming with a Complex but Single-Cycle Instruction Set.", IEEE 1984/89/0000/0526, (1989), pp. 526-533.
Jonathan W. Mills, "A Pipelined Architecture for Logic Programming with a Complex but Single-Cycle Instruction Set.", Technical Report No. 284 from Computer Science Department Indiana University, Bloomington, Indiana (Jul. 1989) pp. 1-28.

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