Reduce 1/f noise in NPN transistors without degrading the...

Details Reduce 1/f noise in NPN transistors without degrading the... Reduce 1/f noise in NPN transistors without degrading the...

2007-03-27

2007-03-27

Andujar, Leonardo (Department: 2826)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C257SE21611

Reexamination Certificate

active

10994563

ABSTRACT:
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.

REFERENCES:
patent: 4575925 (1986-03-01), Kanbara et al.
patent: 5137839 (1992-08-01), Niitsu
patent: 5552626 (1996-09-01), Morikawa
Moiseiwitsch et al., “Improved base current ideality in polysilicon emitter bipolar transistors by fluorine implantation,” IEE Colloquium on Advanced MOS and Bi-Polar Devices, Feb. 14, 1995, IEE, p. 3/1-3/5.
Siabi-Shahrivar et al., “Modeling and characterization of noise polysilicon emitter bipolar transistors,” Proceedings of the IEEE 1990 Bipolar Circuits and Technology Meeting, Sep. 17-18, 1990, IEEE, p. 236-238.
N. Siabi-Shahrivar, et al., “Modeling and Characterization of Noise of Polysilicon Emitter Bipolar Transistors,”IEEE 1990 Bipolar Circuits and Technology Meeting 10.2, pp. 236-238.

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