Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2005-02-15
2005-02-15
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S525000, C257S588000
Reexamination Certificate
active
06856000
ABSTRACT:
An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to reduce the 1/f noise in the NPN transistor.
REFERENCES:
patent: 5137839 (1992-08-01), Niitsu
patent: 5552626 (1996-09-01), Morikawa
N. Siabi-Shahrivar, et al., “Modeling and Characterization of Noise of Polysilicon Emitter Bipolar Transistors,”IEEE 1990 Bipolar Circuits and Technology Meeting 10.2, pp. 236-238.
Kyser, Jr. William F.
Loftin William
Trogolo Joe R.
Brady III W. James
Jackson Jerome
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Reduce 1/f noise in NPN transistors without degrading the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduce 1/f noise in NPN transistors without degrading the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduce 1/f noise in NPN transistors without degrading the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3501693