Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-10-10
2002-04-23
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S777000, C257S723000, C257S691000, C257S784000, C257S786000, C257S665000, C257S664000, C257S737000, C257S738000, C257S778000, C257S724000, C174S050510, C174S050510, C174S050510, C036S181000, C036S181000
Reexamination Certificate
active
06376904
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a multi-chip or stacked integrated circuit (IC) die device. More specifically, this invention is directed toward a multi-chip device having a plurality of IC die, for example, a plurality of memory die, a controller die and memory die, or a processor, controller and plurality of memory die.
One conventional technique employed to provide greater IC densification includes incorporating several IC die into a single package. There is demand for larger IC densification to more fully utilize system layout space for applications such as portable computers and cell phones. An attractive solution is offered by vertical integration of IC die. That is, a three-dimensional approach where IC die are disposed one on top of another to more fully utilize a vertical dimension.
With reference to
FIG. 1
, a conventional multi-chip device
100
having a plurality of IC die
110
and
120
disposed one on top of another is illustrated. IC die
110
is stacked on top of IC die
120
which is disposed on base or substrate
130
. A plurality of bond wires
140
a
-
140
d
electrically couple pads disposed on IC die
110
to pads disposed on IC die
120
. Similarly, a plurality of bond wires
150
a
-
150
m
electrically couple pads disposed on IC die
120
to pads disposed on base
130
.
The physical configuration of multi-chip device
100
tends to relax demands on system layout space. By disposing the IC die (e.g., memory die) vertically, only a single IC die footprint is required thereby resulting in a reduction in system layout space from a lateral or horizontal perspective. Signal lines
140
a
-
140
d
for example, control lines and address/clock lines are routed vertically between the IC die
110
and
120
.
Contemporary stacked die configurations tend to minimize the length of the signal line path. That is, the contemporary approach for stacked die configurations, is to minimize the electrical path length of the signal lines. A stacked die configuration which seeks to minimize the length of the signal lines is described and illustrated in U.S. Pat. Nos. 5,675,180 and 5,698,895.
Contemporary stacked die configurations, like those described and illustrated in U.S. Pat. Nos. 5,675,180 and 5,698,895, employ a minimum signal line path length in order to decrease propagation delay of the signals on those lines. Decreasing the propagation delay between the die tends to increase the speed of operation of the overall system.
In addition to presenting a minimum propagation delay of the signals applied to the signal lines, stacked die configurations employing a minimum signal line path length tend to minimize parasitic capacitance and inductance resulting from the interconnects. In general, this approach may promote faster operation because signal line lengths and corresponding propagation delays are reduced.
FIG. 2A
is a schematic diagram of a plurality of conventional IC die in a stacked die configuration coupled to a signal line employing minimal conductor length between each IC die. Here the plurality of IC die
310
a
-
310
d
are inter-coupled via conductors
320
a
-
320
d
, respectively. Conductors
320
a
-
320
d
represent a signal line. Load capacitances
330
a
-
330
d
represent the load capacitance presented by IC die
310
a
-
310
d
which are coupled to the signal line. In this regard, when electrically coupling IC die to signal bussing, the signal lines become loaded with the inherent load capacitance which is due to the various elements of the I/O structures disposed on the integrated circuit, for example, bond pads, electrostatic discharge protection devices, input buffer transistors, and output driver transistors.
Because the length of conductors
320
a
-
320
d
are minimized, conductors
320
a
-
320
d
exhibit, as a practical matter, negligible inductance. Thus, load capacitances
330
a
-
330
d
are effectively lumped producing an overall equivalent or lumped capacitive characteristic. Here, the capacitive characteristic is present between a ground plane
340
which is common to IC die
310
a
-
310
d
and conductors
320
a
-
320
d.
One method for providing an increase in bandwidth and overall performance of a memory system, is to increase the effective data rate at which data may be transferred to and from each memory device (i.e., the data rate). In memory systems, one conventional approach to achieve such an increase is to increase the clock rate of the system, which tends to increase the data rate of the system and, in turn, the bandwidth.
However, as the data rate increases in multi-chip devices, the lumped capacitive characteristic mentioned above requires increasingly more drive capability from output drivers of the IC die
310
a
-
310
d
to drive data onto conductors
320
a
-
320
c
. That is, as the data rate increases, an increasingly large amount of current is needed in the same given period of time to drive the lumped capacitive characteristic at a faster rate. Driver current for an output driver transmitting on an un-terminated lumped capacitive load is illustrated in FIG.
2
B.
As data rates increase in systems employing minimal or short signal lines between IC die of a stacked die device, the number of IC die which may be coupled along the signal line decreases. As mentioned above, minimal or short signal lines between IC die of a stacked die device tend to result in negligible inductance separating each load capacitance along the signal line. Since each IC die increases the overall lumped load capacitance of the signal line in such a system, the maximum practical number of IC devices which may be coupled to the same signal line tends to become constrained or limited by the drive capability of the drivers on the IC die.
Stacked die configurations employing a minimal conductor length provide relatively fast access times. These configurations, however, suffer a number of shortcomings including a limitation on the maximum practical number of IC devices which may be coupled to the same signal line—i.e., a limit on the amount of vertical integration. Minimum interconnect stacked die configurations place high demands on the output drivers, which imposes an operation speed limitation on the system or a limitation on the number of devices or die coupled to the signal line. Thus, there is a need to provide an effective configuration which has fast access times, increases the operation speed of a multi-chip or stacked die device, and provides more flexibility in vertical integration.
SUMMARY OF THE INVENTION
A semiconductor module has a first integrated circuit die having a planar surface. The first integrated circuit die comprises a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module further has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.
A semiconductor module is made from existing integrated circuit dice by redistributing a first conductive pad disposed substantially on a planar surface of a first integrated circuit die to a redistributed conductive pad disposed near a periphery of the planar surface. This may be undertaken by applying a conductive layer to the planar surface of the first integrated circuit die, and forming a redistributed conductive pad and a conductive trace from the conductive layer, where the conductive trace electrically connects the first conductive pad and the redistributed conductive pad. A second integrated circuit die is then stacked adjacent to the planar surface and offset from the periphery. Finally, a second conductive pad on the second integrated circuit die is electrically connected to the redistributed conductive pad.
REFERENCES:
patent: 4879588 (1989-11-01), Ohtsuka et al.
patent: 5703436 (19
Haba Belgacem
Khalili Sayeh
Perino Donald V.
Pennie & Edmonds LLP
Rambus Inc.
Williams Alexander O.
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