Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-05-31
2001-11-20
Lam, Tuan T. (Department: 2816)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S172000
Reexamination Certificate
active
06320530
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a recycling A/D converter capable of implementing the A/D converting processing including not less than three steps.
As disclosed in the Japanese Patent publication No. 6-83069 or in the IEEE Journal of Solid-state Circuits, Vol. 25, No. 6, December 1990, pp1328-PP1338, one of this kind of recycling A/D converters is a so-called two step recycling A/D converter which includes a capacitor array circuit (i.e., an array of capacitors), an operational amplifier, a capacitor connected between the input and output terminals of the operational amplifier, and an A/D conversion circuit of a parallel type.
FIG. 11
shows a circuit arrangement of a 2-step recycling A/D converter. An A/D conversion circuit
1
of a parallel type has an input terminal selectively connectable to a signal input terminal
2
or an output terminal of an operational amplifier
3
via a switch S
8
. A capacitor array circuit
4
comprises a plurality of arrayed capacitors C
0
to C
7
which have common electrodes respectively connected to a common line
5
. The arrayed capacitors C
0
to C
7
have non-common electrodes respectively connectable via switches S
0
to S
7
to one of the input terminal of the A/D conversion circuit
1
, a reference voltage terminal
6
, and a ground terminal GND. The operational amplifier
3
has an inverting input terminal connected to the common line
5
. A capacitor CF and a switch S
9
are connected in parallel with each other between the input and output terminals of the operational amplifier
3
.
In this circuit arrangement, the A/D conversion circuit
1
implements a first step A/D conversion under a condition where the switch S
8
is connected to the input terminal of the A/D conversion circuit
1
, while the switches S
0
to S
7
are respectively connected to the input terminal of the A/D conversion circuit
1
and the switch S
9
is turned on.
After the first step A/D conversion is completed, the switch S
9
is turned off. Respective switches S
0
to S
7
are shifted to either the reference voltage terminal
6
or the ground terminal GND in accordance with an A/D conversion code resulting from the first step A/D conversion. As a result, the operational amplifier
3
produces an output voltage equivalent to a residue voltage of the first step A/D conversion result. Then, the switch S
8
is shifted to the output terminal of the operational amplifier
3
. The A/D conversion circuit
1
implements a second step A/D conversion. An adder
7
adds the A/D conversion code of the first step and the A/D conversion code of the second step, thereby producing an A/D conversion output having a resolution higher than that of the A/D conversion circuit
1
.
According to the above-described conventional 2-step recycling A/D converter, the circuit scale of the A/D conversion circuit
1
and the capacitor array circuit
4
expands in proportion to the enhancement of resolution (i.e., bit number). This leads to an undesirable increase of the chip size.
SUMMARY OF THE INVENTION
To reduce the required resolution level in each step, it is effective to replace the above-described conventional 2-step A/D converter by a recycling A/D converter capable of implementing the A/D conversion processing including not less than three steps. In addition to the chip size, consumption of electric power will be greatly reduced.
If the above-described conventional 2-step A/D converter is directly used to implement the third and succeeding conversion operations, electric charge of the capacitor CF will transfer to the arrayed capacitors C
0
to C
7
upon connecting the output terminal of the operational amplifier
3
to the non-common terminals of the arrayed capacitors C
0
to C
7
via the switches S
0
to S
7
. This will cause an undesirable change in the output voltage level of the operational amplifier
3
.
To eliminate this problem, it may be effective to provide a sample-and-hold circuit connected to the output terminal of the operational amplifier
3
. In this case, the sample-and-hold circuit holds the output voltage of the operational amplifier
3
. Charge setting for the arrayed capacitors C
0
to C
7
is performed based on the voltage value held by the sample-and-hold circuit.
However, providing the sample-and-hold circuit in the recycling loop is not preferable in that an error is newly produced from the sample-and-hold circuit. For example, an error of the sample-and-hold circuit is derived from an offset voltage of an operational amplifier which serves as an essential circuit component of the sample-to-hold circuit. The error thus produced is cumulatively accumulated through the repetition of steps of the conversion processing. As a result, the resultant conversion error will become large. On the other hand, it is generally difficult for manufacturers to predict such a conversion error at an earlier stage (for example, in the design stage of the circuit). Furthermore, providing the sample-and-hold circuit necessarily expands the circuit size due to additional circuit components (e.g., the operational amplifier and the hold capacitor) constituting the sample-and-hold circuit. Accordingly, the chip size increases correspondingly and the consumption of electric power increases too.
In view of the above, an object of the present invention is to provide a novel recycling A/D converter which is compact in chip size and is capable of accurately implementing the A/D conversion processing including not less than three steps.
In order to accomplish this and other related objects, a recycling A/D converter of the present invention comprises an A/D conversion circuit, and a capacitor array circuit comprising a plurality of arrayed capacitors. Each arrayed capacitor has a common electrode connected to a common line and a non-common electrode selectively connectable to either a first reference voltage line or a second reference voltage line in response to a conversion result of the A/D conversion circuit. An operational amplifier has an input terminal connected to the common line. An integrating capacitor is connected between the input terminal and an output terminal of the operational amplifier. An integration initializing circuit is provided for initializing the integrating capacitor. A circuit arrangement is provided for inputting an output voltage of the operational amplifier to the A/D conversion circuit and to the non-common electrodes of the arrayed capacitors. A first switching circuit is provided between the common line and the input terminal of the operational amplifier. And, a second switching circuit is provided between the common line and the first reference voltage line.
According to the recycling A/D converter of the present invention, in the A/D conversion of a third or succeeding step, charge setting of each arrayed capacitor is implemented based on the output voltage of the operational amplifier by closing the second switching circuit under a condition where the first switching circuit is opened, and then the integrating capacitor is initialized by the integration initializing circuit.
With this circuit arrangement, it becomes possible to make the operational amplifier connected to the integrating capacitor act as a hold circuit by opening the first switching circuit provided between the common line and the input terminal of the operational amplifier. Furthermore, as the second switching circuit is provided between the common line and the first reference voltage line, it becomes possible to implement the charge setting of the arrayed capacitors based on the output voltage of the operational amplifier by closing the second switching circuit even when the first switching circuit is opened.
In the third and succeeding steps of the conversion processing, it is necessary to perform the charge setting of the arrayed capacitors and the initialization of the integrating capacitor based on the principle of the charge redistribution as one preprocessing for obtaining the residue voltage with respect to the conversion result of the A/D conversio
Denso Corporation
Lam Tuan T.
Law Offices of David G. Rose
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