Recursive-type digital filter with reduced round-off noise

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364745, G06F 738

Patent

active

043375189

ABSTRACT:
A recursive-type digital filter comprising a calculation circuit. The calculation circuit is arranged to multiply an input signal including at least m-bit signal x.sub.n inputted at a predetermined sampling period and an output signal y.sub.n-k fed back to the input of the calculation circuit in accordance with the input signal x.sub.n after being subjected to a delay of k sampling periods by a.sub.k and b.sub.k coefficients corresponding to the filter characteristics, respectively, and then the products are added thereby to produce data y.sub.n of (m+l) bits satisfying, ##EQU1## and serially deliver the upper m-bit data of the data y.sub.n as an output signal corresponding to the input signal x.sub.n.
The filter further comprises a delay circuit for feeding back to the input of the calculation circuit a part of the round off data including the upper (m+1)th bit of the data y.sub.n so that the b.sub.k coefficient is multiplied by the fedback data of the upper (m+1)th bit and the product is added to the data y.sub.n, thereby to produce an output signal with reduced round off noise.

REFERENCES:
patent: 3777130 (1973-12-01), Crorsier et al.
patent: 3982112 (1976-09-01), Schlereth
patent: 4034196 (1977-07-01), Butterweck et al.

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