Rectifier circuit suited to power factor correction

Details Rectifier circuit suited to power factor correction Rectifier circuit suited to power factor correction

2002-03-07

2004-08-17

Leja, Ronald (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With tuned circuit

C315S247000, C363S044000

Reexamination Certificate

active

06778373

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a rectifier circuit matched for power factor correction, comprising a first diode, a second diode, a third diode and a fourth diode in bridge arrangement, an inductance and a capacitance, with a first pole and a second pole of the bridge arrangement being connected to a source which has at least one AC voltage component, and the inductance being arranged in series with the third pole or the fourth pole.
BACKGROUND OF THE INVENTION
Such apparatuses are known from the prior art and are shown by way of example in
FIGS. 1
a
to
1
d.
The problem on which the invention is based will be presented with reference to the circuits in
FIGS. 1
a
to
1
d
. From 2001 onward, it is a requirement of IEC 1000-3-2 that mains current harmonics also be observed for systems with mains power of less than 25 W. An ever growing number of lamp types requires the use of electronic equipment whose second stage downstream of the spark suppression filter is a mains rectifier. In order to observe IEC 1000-3-2, power factor correction, PFC for short, is required.
FIG. 1
a
shows a mains rectifier known from the prior art which is designed for subsequent power factor correction. In this case, the mains rectifier comprises four diodes D
1
to D
4
in bridge arrangement. The bridge arrangement comprises a first pole
10
, a second pole
12
, a third pole
14
and a fourth pole
16
, the poles
10
and
12
being connected to a source which has at least one AC voltage component. The poles
14
and
16
are connected to one another via a capacitance C
1
, the capacitance C
1
preferably being small, in particular in the region of a few dozen nF. The pole
16
is connected to ground, while the pole
14
is first followed by a diode D
5
, and then by an inductance L
1
. The arrow
18
points in the direction of the rest of the circuit, with, in particular, a relatively large storage capacitance coming next in the direction of the arrow, which storage capacitance then supplies the equipment with DC voltage. It is particularly advantageous, as shown in the present case, for the mains rectifier to be connected to an inductance so that it is suitably loaded. The PFC circuit also contains at least one switching element (not shown) switching at a high frequency, which switching element controls the mains current such that it becomes as proportional as possible to the voltage, that is to say sinusoidal in most cases.
A drawback for the operation of PFC is if the switching voltages of this high frequency switching element rise via the inductance L
1
and reverse currents flow into the mains rectifier—the wrong way round, so to speak. Specifically, the result of this would be that the capacitor C
1
is charged by the reverse current, and a current hole therefore arises in the current drawn from the mains, i.e. no current is drawn for a particular period of time. This is possible because the duration of the turnoff reverse currents in the slow mains diodes D
1
to D
4
corresponds to approximately half a period duration of the switching element switching at high frequency in the PFC circuit. As a countermeasure, the output of the mains rectifier having the diodes D
1
to D
4
has an additional, albeit fast, diode D
5
connected to it in series with the PFC inductance, downstream of the small capacitance C
1
.
The block
20
combines the elements which make up the PFC circuit.
FIG. 1
b
shows a slightly modified variant in which the fast diode D
5
is connected between the pole
16
and the ground, while the inductance is connected directly to the pole
14
. In the circuit shown in
FIG. 1
c
, the pole
16
is connected to ground via the inductance L
1
, while the fast diode D
5
is arranged at the pole
14
. In the circuit shown in
FIG. 1
d
, the series circuit comprising the fast diode D
5
and L
1
is arranged between pole
16
and ground.
SUMMARY OF THE INVENTION
On the basis of these circuits known from the prior art, the object on which the present invention is based is to develop a generic rectifier circuit such that it can be produced using fewer components, in particular that the diode D
5
can be dispensed with.
A rectifier circuit matched for power factor correction. A first diode (D
1
), a second diode (D
2
), a third diode (D
3
) and a fourth diode (D
4
) are in a bridge arrangement. A first pole (
10
) and a second pole (
12
) of the bridge arrangement are connected to a source (U) which has at least one AC voltage component. An inductance (L
1
) is arranged in series with the third pole (
14
) or the fourth pole (
16
) of the bridge arrangement. A capacitance (C
1
) is connected between the first pole (
10
) and the second pole (
12
), and two of the four diodes (D
1
, D
2
, D
3
, D
4
) are in the form of fast diodes.
The invention is based on the idea that the diode D
5
can be replaced by virtue of two of the four diodes of the rectifier being in the form of fast diodes, with the capacitance C
1
then needing to be connected between the first pole and the second pole. This measure eliminates the need for the fifth diode. Another advantage is obtained by virtue of the capacitance simultaneously acting as x-capacitor for spark suppression.
In one particularly preferred embodiment, the capacitance C
1
is formed by a first capacitance element and a second capacitance element connected in series, the junction point between the first capacitance element and the second capacitance element being connected to the third pole or to the fourth pole of the bridge arrangement. This measure affords the advantage that it allows the individual potentials to be defined even more reliably with respect to RF voltage. In this context, the junction point between the two capacitance elements is preferably connected to the pole which is common to the two slow diodes.
Irrespective of whether or not the capacitance C
1
is split into capacitance elements, the following four particularly preferred embodiments can be implemented:
In this regard, the first diode may be connected between the first pole and the third pole, the second diode may be connected between the first pole and the fourth pole, the third diode may be connected between the fourth pole and the second pole and the fourth diode may be connected between the second pole and the third pole. The first embodiment is then distinguished in that the first diode and the fourth diode are in the form of fast diodes, the inductance is arranged in series with the third pole, and the fourth pole is connected to ground. In the second embodiment, the second diode and the third diode are in the form of fast diodes, the inductance is arranged in series with the third pole, and the fourth pole is connected to ground. In the third embodiment, the first diode and the fourth diode are in the form of fast diodes, the inductance is arranged in series with the fourth pole, and the fourth pole is connected to ground via the inductance. In the fourth embodiment, the second diode and the third diode are in the form of fast diodes, the inductance is arranged in series with the fourth pole, and the fourth pole is connected to ground. The diodes which do not explicitly need to be in the form of fast diodes can be in the form of slow diodes.
In this context, fast diode means that the duration of the turnoff reverse current is from 10 ns to 100 ns. A slow diode is referred to when the duration of the turnoff reverse current is between 1 &mgr;s and 20 &mgr;s.


REFERENCES:
patent: 5459375 (1995-10-01), Nilssen
patent: 5959849 (1999-09-01), Batarseh et al.
patent: 5986898 (1999-11-01), Meitzner et al.
patent: 6005780 (1999-12-01), Hua
patent: 197 47 801 (1999-05-01), None
Maset et al, “Harmonic reduction in low-cost power supplies”, Power Electronics Congress, 1996, Technical Proceedings, CIEP '96., V IEEE, International Cuernavaca, Mexico 14-17, Oct. 1996, New York, NY USA, IEEE; US; Oct. 14, 1996; pp. 15 21; XP010244348; ISBN: 0-7803-3633-X.
Jiang Lee Yimin et al, “Single-stage single-phase parallel power factor correction scheme”, Pow

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