Pulse or digital communications – Receivers
Reexamination Certificate
2000-10-20
2004-08-31
Fan, Chieh M. (Department: 2634)
Pulse or digital communications
Receivers
C375S329000
Reexamination Certificate
active
06785343
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to rectangular-to-polar conversion in communication systems employing digital words, and more specifically relates to such conversion in which a portion of the digital words representing rectangular coordinates are truncated.
Rectangular-to-polar converters have been known in the past. One such angle converter
10
is shown in
FIGS. 1 and 2
. Referring to
FIG. 1
, converter
10
receives an I input on a 24-bit bus
12
and a Q input on a 24-bit bus
14
. The I and the Q 24-bit words represent an angle in rectangular coordinate form. The sign bits of the I and Q input words are removed by sign bit removers
20
and
21
. The sign bit is the most significant bit of the input I and Q words in which zero represents positive and 1 represents negative. The resulting 23-bit words are converted to their absolute values in circuits
30
and
31
which also map the phase angle represented by the input I and Q words into the first quadrant (0-90 degrees).
At various points in converter
10
, the digital words are transmitted through delay registers
40
-
63
. Additional delay registers
64
-
66
are sufficient in number to equal the pipeline delay of a normalizer
70
which is described in more detail on FIG.
2
.
After the digital I and Q words are transmitted through registers
40
and
41
, they are subtracted by a subtractor
80
and subjected to a comparator
84
which determines whether the I word or the Q word is larger. The I and the Q words are then transmitted through registers
42
and
43
and processed by a swap circuit
86
. After further processing, the words are also processed by a similar swap circuit
87
.
Swap circuit
86
places the I or Q word with the larger value as determined by comparator
84
on output
88
.
After transmission through registers
44
and
45
, the I and Q words are processed by normalizer
70
which truncates 19 of the 23 bits in the input words in the manner later described in connection with FIG.
2
.
After transmission through registers
46
and
47
, the truncated I and Q words are processed by swap circuit
87
which corresponds to outputs truncated version of I input (corresponding to bus
12
) to register
48
and truncated version, of Q input (corresponding to bus
14
) to register
49
if the I, Q input lies in quadrant 1 or 3 in the Cartesian plane. If the I, Q input lies in quadrant 2 or 4 in the Cartesian plane, swap circuit
87
outputs truncated version of Q input (bus
14
) to register
48
and truncated version of I input (bus
12
) to register
49
.
After transmission through registers
48
and
49
, the truncated I and Q words are used to address a signal generator, such as a phase angle read-only memory (ROM)
90
. Since the original 23 bits of the I and Q words were truncated by normalizer
70
, a single value of the resulting truncated words represent a larger range of phase angles than a single value of the original 23 bit I and Q words. According to the prior art, the integer value of the truncated words used to address the phase ROM was increased by 0.5 for both the I and Q words. Phase ROM
90
estimated the angle of the input I and Q words based on the truncated value increased by 0.5, and produced a resulting word indicating phase angle in polar coordinates on an output conductor
91
.
The phase angle indicating word on conductor
91
was restored to its original quadrant by an offset read only memory
94
. After passing through a register
50
, the phase angle indicating digital word was transmitted over an output conductor
96
.
Referring to
FIG. 2
, normalizer
70
comprises input buses
108
-
109
, output buses
171
-
172
and multiplier circuits
110
-
119
which multiply the input value by an amount indicated by the power of 2 drawn immediately above the multiplier symbol in FIG.
2
. Normalizer
70
also includes truncation functions
130
-
139
which truncate the number of most significant bits indicated immediately below the function symbol in FIG.
2
.
Normalizer
70
also includes OR gates
142
-
145
connected as shown. Two to one multiplexers
150
-
159
transmit digital words conducted either to their top input or bottom input depending on a control signal. For example, referring to multiplexer
150
, if the control signal on control conductor
125
represents a 1, then the input signal on input bus
126
is transmitted through multiplexer
150
. On the other hand, if the value of the signal on conductor
125
represents a zero, then the input signal on bus
127
is conducted through multiplexer
150
. The other multiplexers
151
-
159
operate in the same manner as multiplexer
150
.
Normalizer
70
also includes delay registers
162
-
169
connected as shown.
In operation, normalizer
70
, attempts to locate the most significant bit (MSB) of the
23
bit word transmitted on bus
108
which has a value of 1. The most significant bit with a value of 1, and the next three MSBs, are delayed and saved so that they appear on output
171
and are not truncated. If none of the 19 most significant bits of the input word on bus
108
has a value of 1, then the four least significant bits on input
108
are transmitted to the output on bus
171
. The corresponding bits in the words transmitted to input
109
are treated the same as the bits transmitted to input
108
.
The phase ROM
90
described in connection with
FIG. 1
added a constant value to the integer represented by its inputs, more specifically, the value 0.5. This resulted in degraded accuracy. This invention addresses that deficiency and offers a solution.
BRIEF SUMMARY OF THE INVENTION
The preferred embodiment is useful in a communication system for converting phase information represented by digital words from rectangular form to polar form. In such an environment, an input receives one or more digital words representing an original phase angle in rectangular form. The input digital words are truncated by a plurality of bits to form truncated words. A variable phase signal representing a resultant phase angle range is generated and depends at least in part on the number of the bits truncated. The resultant phase angle range includes the original phase angle.
By using the foregoing techniques, phase information may be changed from rectangular to polar form with a degree of accuracy and economy previously unattainable.
REFERENCES:
patent: 3575593 (1971-04-01), Staples
patent: 5295162 (1994-03-01), Zarembowitch
patent: 6084923 (2000-07-01), Cullen
patent: 6255906 (2001-07-01), Eidson et al.
Fan Chieh M.
Northrop Grumman Corporation
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