Recovery circuit generating low jitter reproduction clock

Details Recovery circuit generating low jitter reproduction clock Recovery circuit generating low jitter reproduction clock

2001-07-05

2003-05-13

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C327S156000

Reexamination Certificate

active

06563355

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a recovery circuit generating a reproduction clock in synchronism with received data in a receiving section of a communication apparatus and particularly, to a recovery circuit generating a low jitter reproduction clock.
2. Description of the Background Art
A recovery circuit generating a reproduction clock based on received data in a receiving section of a communication apparatus transmitting/receiving data compares a phase of reproduction clock with a phase of received data to have the reproduction clock to be synchronized with the received data. Received data in the receiving section is a NRZ (Non-Return Zero) signal and a reproduction clock is a RZ (Return Zero) signal; therefore comparison of both in phase has to be performed at edges of the data.
Referring to
FIG. 24
, a conventional phase comparator circuit
500
included in a recovery circuit is constituted of: flip-flops
510
and
520
; and EX-OR gates
530
and
540
. The flip-flop
510
is driven in synchronism with the rising edge of a reproduction clock CLK, receives received data DIN as an input signal to output output signals to the flip-flop
520
and the EX-OR gates
530
and
540
. The flip-flop
520
is driven in synchronism with the falling edge of the reproduction clock CLK, receives an output signal of the flip-flop
510
and outputs an output signal to the EX-OR gate
540
. The EX-OR gate
530
receives the received data and an output signal of the flip-flop
510
as input signals, performs an exclusive OR operation on the two input signals to output an up signal UP. Further, the EX-OR gate
540
receives an output signal of the flip-flop
510
and an output signal of the flip-flop
520
as inputs, performs an exclusive OR operation on the two signals to output a down signal DWN.
Referring to
FIG. 25B
, when a reproduction clock CLK is delayed as compared to received data in phase, the flip-flop
510
outputs a signal D
1
in synchronism with the rising edge of the reproduction clock CLK, while the exclusive OR gate
530
performs an exclusive OR operation on the received data DIN and the signal D
1
to output an up signal UP. Further, the flip-flop
520
holds the output signal D
1
of the flip-flop
510
in synchronism with the falling edge of reproduction clock CLK to output a signal D
2
. The exclusive OR gate
540
performs an exclusive OR operation on the signals D
1
and D
2
to output a down signal DWN. In this case, a width of the up signal UP is larger than that of the down data DWN. Accordingly, when the reproduction clock CLK is delayed as compared to the received data DIN in phase, the phase comparator circuit
500
outputs the up signal UP with a larger width.
Further, with reference to
FIG. 25C
, when reproduction clock CLK leads received data DIN in phase, a width of a down signal is larger than that of an up signal UP. Accordingly, when the reproduction clock CLK leads the received data DIN in phase, the phase comparator circuit
500
outputs a down signal DWN with a larger width.
Referring to
FIG. 25A
, when a phase of a reproduction clock CLK coincides with a phase of received data DIN, the phase comparator circuit
500
outputs an up signal UP and a down signal DWN, both of the same width.
That is, the phase comparator circuit
500
outputs an up signal UP and a down signal DWN, when an edge of received data is inputted, in any of cases where in phase, a reproduction clock CLK is delayed as compared to received data DIN, leads data DIN and coincides with data DIN. When reproduction clock CLK is delayed as compared to received data DIN in phase, a phase of the reproduction clock CLK is adjusted such that a width of an up signal is narrowed and comes to be the same as that of a down signal. Further, when reproduction clock CLK leads received data in phase, a phase of the reproduction clock CLK is adjusted such that a width of a down signal DWN is narrowed and comes to be the same as that of an up signal UP.
Phase adjustment of a reproduction clock is performed by an operation in which a control voltage based on a comparison result in phase of the phase comparator circuit
500
is outputted to a voltage controlled oscillator and a phase of the reproduction clock CLK is altered according to a level of the control voltage. That is, a capacitor is connected between an output node supplying a control voltage to the voltage controlled oscillator and a ground node, an electric charge corresponding to a width of an up signal is charged in the capacitor to raise the control voltage or an electric charge corresponding to a width of a down signal is discharged from the capacitor to lower the control voltage, whereby the control voltage is adjusted such that a phase of a reproduction clock CLK coincides with a phase of received data DIN.
Hence, when reproduction clock CLK is delayed as compared to received data DIN in phase, charging of the capacitor by an up signal UP and discharging of the capacitor by a down signal DWN are alternately repeated and in such repetitions of charging and discharging, a charge time of the capacitor by up signals is adjusted to be totally longer than a discharge time of the capacitor by down signals, with the result that the control voltage gradually rises. Further, when a reproduction clock CLK leads received data DIN in phase, charging of the capacitor by an up signal UP and discharging of the capacitor by a down signal DWN are alternately repeated and in such repetitions of charging and discharging, a discharge time of the capacitor by down signals DWN is adjusted to be totally longer than a charge time of the capacitor by up signals UP, with the result that the control voltage gradually falls. Still further, when a phase of reproduction clock CLK coincides with a phase of received data DIN, charging of the capacitor by up signals UP and discharging of the capacitor by down signals DWN are alternately repeated such that a charge time of the capacitor by up signals UP and a discharge time by down signals DWN are totally equal to each other and as a result, the control voltage is held unchanged, as a whole, though process.
In a prior art recovery circuit, however, even when a phase of a reproduction clock CLK coincides with a phase of received data DIN, an up signal and a down signal are repeatedly outputted at edges of received data; therefore charging of the capacitor by up signals UP and discharging of the capacitor by down signals DWN are repeated such that a control voltage supplied to a voltage controlled oscillator is held at a constant value. With such an operation adopted, when intervals between the charging and the discharging are gradually longer, a problem arose since the timing of voltage adjustment in the voltage controlled oscillator is shifted, thereby producing jitter in the reproduction clock CLK.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve such a problem and it is accordingly an object of the present invention is to provide a recovery circuit capable of generating a low jitter recovery clock regardless of an operating frequency.
A recovery circuit according to the present invention includes: a phase comparator circuit comparing a phase of a reproduction clock with a phase of received data, outputting an up signal when the reproduction clock is delayed as compared to the received data in phase and an edge of the received data has been detected in a first period in which the reproduction clock is a first logic, and outputting a down signal composed of a first component having detected an edge of the received data in a second period in which the reproduction clock is a second logic and a second component having detected that a logic of the received data is constant in the second period when the reproduction clock leads the received data in phase; a control voltage adjusting circuit raising a control voltage when the up signal is inputted, lowering the control voltage when the first component of the down signal is inputted and

Affiliated with

Also associated with

Rating

Recovery circuit generating low jitter reproduction clock does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Recovery circuit generating low jitter reproduction clock, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Recovery circuit generating low jitter reproduction clock will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3080199