Recovering phase and data from distorted duty cycles caused by E

Details Recovering phase and data from distorted duty cycles caused by E Recovering phase and data from distorted duty cycles caused by E

1992-08-28

1993-11-23

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, H03K 190175, H03K 19003

Patent

active

052647455

ABSTRACT:
A logic interface circuit for recovering phase and data information from ECL differential input signals of the NRZI type having distorted duty cycles caused by ECL-to-CMOS translators includes first and second ECL-to-CMOS translators (T1, T2), first and second delay circuits, and an output logic circuit The first delay circuit is formed of a first inverter (I1), a first delay network (D1), and a first NAND logic gate (N1). The second delay network includes a second inverter (I2), a second delay network (D2), and a second NAND logic gate (N2). The output logic circuit is formed of a third NAND logic gate. The interface circuit generates an output signal which is in the form of a pulse train whose cycle time can be detected for determining the frequency information and whose presence or absence of pulses can be detected for determining data information.

REFERENCES:
patent: 4140980 (1979-02-01), Cummings
patent: 4798981 (1989-01-01), Tsugaru et al.
patent: 4868425 (1989-09-01), Lindenfelser
patent: 4958132 (1990-09-01), Plants

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