Electrical pulse counters – pulse dividers – or shift registers: c – Charge transfer device
Patent
1994-07-08
1995-03-07
Rosenwambach, Margaret
Electrical pulse counters, pulse dividers, or shift registers: c
Charge transfer device
257235, 331117R, 327530, 327544, 327284, 326 93, G11C 1928
Patent
active
053965272
ABSTRACT:
A logic circuit is driven by a single alternating voltage power supply so that the energy stored in parasitic capacitances can be mostly recovered, rather than dissipated, as in conventional logic designs. Successive stages of the logic circuit are of opposite conductivity types such that the successive stages are activated in alternate half cycles of the power supply without separate clock signals. Each stage of the logic circuit is precharged during a respective first half cycle of the power supply and is active in logical processing during a second half cycle. The half cycles are defined by the rising and falling edges of the power supply. The logic circuit resonates with an inductor coupled across the power supply but closely coupled to the logic circuit. This inductor and the method of charging and discharging the capacitors in the logic circuit serve to minimize the power dissipated during logical processing.
REFERENCES:
patent: 3651334 (1972-03-01), Thompson et al.
patent: 4190778 (1980-02-01), Krause
patent: 4996454 (1991-02-01), Peczalski et al.
Boysel, Lee L. et al., "Four-Phase LSI Logic Offers New Approach to Computer Designer," Computer Design, Apr. 1970, pp. 141-146.
Yang, Long et al., "High Speed Dynamic Circuits Implemented with GaAs Mesfets,", IEEE, 1987, GaAs IC Symposium, pp. 261-263.
Lu, Shih-Lien, "A Safe Single-Phase Clocking Scheme for CMOS Circuits," IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 280-283.
Seitz, Charles L. et al., "Hot-Clock nMOS," Department of Computer Science, California Institute of Technology, Pasadena, 1985 Chapel Hill Conference on VLSI, pp. 1-17.
Yap, Jee-Hoon, Bachelor's Thesis, "Low Power Digital Circuits Using AC-Power," Submitted to the Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology.
Titow, W. A., "Transistorlogik mit Wechselstrom," NACHRICHTENTECHNIK, vol. 20, No. 5, May 1970, Berlin, pp. 171-179.
Patent Abstracts of Japan, vol. 3, No. 156 (E-161) 21 Dec. 1979, (Matsushita Dengi Sangyo K.K.) 26 Oct. 1979.
Hinman, Roderick, "Recovered Energy Logic: A Logic Family and Powr Supply Featuring Very High Efficiency," Doctoral Thesis, Massachusetts Institute of Technology, May 1994, pp. 1-231.
Ji-Ren, Yuan et al., "A True Single-Phase-Clock Dynamic CMOS Circuit Technique," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 899-901.
Yuan, Jiren et al., "High-Speed CMOS Circuit Technique," IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 62-70.
Afghahi, Morteza et al., "A Unified Single-Phase Clocking Scheme for VLSI Systems," IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, pp. 225-231.
Penney, MOS Integrated Circuits, Von Nostrand 1972, pp. 265-289.
Patel, D. C., "Novel design of the output stage for four-phase dynamic VLSI logic," Microelectronics Journal, vol. 15, No. 3 1984 Benn Electrnoics Publications Ltd, Luton, pp. 12-17.
Glasser & Dobberpuhl, The Design & Analysis of VLSI Circuits, Addison-Wesley, 1985, p. 61.
Teggatz, Ross E., "A Power-Efficient 32-Bit Electroluminesecent Display Column Driver," Society for Information Display, International Symp., Digest of Technical Papers, vol. XX, Playa del Rey, Calif., 1989, pp. 68-70.
Svensson, K. "J", et al., Adiabatic charging without inductors, University of Southern California, Information Sciences Institute, Marina del Rey, Calif. 90292, Feb. 8, 1994, pp. 1-20.
Athas, W. C., et al., "An Energy-Efficient SMOS Line Driver Using Adiabatic Switching," University of Southern California, Information Sciences Institute, Marina del Rey, Calif. 90292, Jul. 30, 1993, pp. 1-16.
Younis, Saed, et al., "Asymptotocally Zero Power Split-Level Charge Recovery Logic,"]MIT Artificial Intelligence Laboratory, Cambridge, Mass. 02139, unpublished, 4 pgs.
Younis, Saed, et al., "Practical Implementation of Charge Recovering Asymptotically Zero Power CMOS," 1993 Symposium on Integrated Systems, MIT Press, 1993, pp. 234-250.
Hall, J. Storrs, "An Electroide Switching Model for Reversible Computer Architectures," Proceedings of the Workshop on Physics of Computation, Oct. 1992, Published by IEEE Press, 1993, pp. 1-15.
Koller, Jeffrey G., "Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information," Proceedings of the Workshop on Physics of Computation, Oct. 1992, IEEE Press pp. 1-7.
Denker, John S. et al., "Adiabatic Computing with the 2N-2N2D Logic Family," IWLPD '94 Workshop Proceedings, International Workshop on Low Power Design, Apr. 1994, pp. 183-187.
Hinman Roderick T.
Schlecht Martin F.
Massachusetts Institute of Technology
Rosenwambach Margaret
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