Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2002-12-19
2004-02-03
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S428000, C370S394000, C370S401000, C370S413000
Reexamination Certificate
active
06687256
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to network management and control; and, more particularly to packet processing and flow determination.
2. Description of the Background Art
Current technology provides packet-switched networks, in which relatively small units of data called packets are delivered via the network to a destination address contained within each packet. Breaking communication down into packets allows the same data path to be shared among many users in the network. Most traffic over the Internet uses packet switching; therefore, the tremendous volume of Internet traffic results in a great magnitude of packet processing activity.
Packet processing, however, brings about issues of flow determination, particularly with regard to header lookup latencies; i.e., the delay in packet distribution incurred when the system processes packet header information to determine flow priority. Memory bandwidth is a critical aspect in any packet processing flow. As such, speculatively storing packet data into buffers hides header lookup latencies for flow determination, yet contributes to buffer overflow conditions.
What is needed, therefore, is a speculative packet disposition scheme with automatic recovery to alleviate the lookup delay associated with the determination of eligibility for cut through, while minimizing buffer overfill.
SUMMARY OF THE INVENTION
The present invention addresses the issue of the prior art and current art with a system and method for a speculative packet disposition scheme with automatic recovery. A “cut through” buffer (CTB) mechanism and system is proposed to reduce the synchronized dynamic random access memory (SDRAM) latency. The system and method provide support for pass through or store and forward of packets, including automatic recovery functionality. A two-way multithreaded implementation hides the latency of the eligibility determination process for packet forwarding operations to eliminate or minimize adverse performance issues associated with buffer overfill and processing latency.
In one embodiment, a method includes the steps of speculatively enqueueing duplicate packet data in packet memory and a cut through buffer; reading label information with a control unit from static random access memory (SRAM); determining if the packet is to remain enqueued in packet memory or cut through based on preexisting criteria; and, based on the determination made in the prior step, rolling back the ineligible enqueued process.
In another embodiment, a system comprises a cut through buffer having at least one basic unit having packet memory and packet descriptor, and a control unit for determining cut through eligibility.
Further advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.
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Modali Prasad
Nangunoori Anil Babu
Saxena Nirmal Raj
Alliance Semiconductor Corporation
Chin Wellington
Ho Chuong
LaRiviere Grubman & Payne, LLP
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