Static information storage and retrieval – Analog storage systems
Reexamination Certificate
2002-04-08
2003-02-25
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Analog storage systems
C365S185110, C365S230030
Reexamination Certificate
active
06525952
ABSTRACT:
TECHNICAL FIELD
The invention relates to a recording system, a data recording apparatus, a memory apparatus, and a data recording method, in which a memory card which is detachable to/from an apparatus is used as a recording medium.
BACKGROUND ART
According to an electrically rewritable non-volatile memory called EEPROM (Electrically Erasable Programmable ROM), since one bit is constructed by two transistors, an occupation area per bit is large and there is a limitation in case of raising an integration degree. To solve such a problem, a flash memory in which one bit can be realized by one transistor by an all-bit batch erasing method has been developed. The flash memory is expected as a memory which can be substituted for a recording medium such as magnetic disk, optical disk, or the like.
It is known that a memory card having a flash memory is constructed so as to be detachable to/from an apparatus. By using such a memory card, a digital audio recording and reproducing apparatus using the memory card in place of the conventional disk-shaped medium such as CD (Compact Disc), MD (Minidisc), or the like can be realized. Besides audio data, still image data and motion image data can be also recorded into the memory card and it can be used as a recording medium of a digital still camera or a digital video camera.
According to the flash memory, a data unit called a segment is divided into a predetermined number of clusters (fixed length) and one cluster is divided into a predetermined number of sectors (fixed length). The cluster is also called a block. The sector is also called a page. In the flash memory, an erasure is performed in a lump on a cluster unit basis, and the writing or reading operation is performed in a lump on a sector unit basis.
For example, in case of the flash memory of 4 MB (megabytes), as shown in
FIG. 12
, one segment is divided into 512 clusters. The segment is a unit for managing a predetermined number of clusters. One cluster is divided into 16 sectors. One cluster has a capacity of 8 kB (kilobytes). One sector has a capacity of 512 B. A memory of a capacity of 16 MB can be constructed by using four segments each having a capacity of 4 MB.
As shown in
FIG. 13A
, logic cluster addresses are allocated to a memory space of 16 MB. The logic cluster address is set to a length of 2 bytes in order to distinguish 512×4=2048 clusters. In
FIG. 13
, the logic cluster address is expressed by a hexadecimal number. 0x denotes the hexadecimal notation. A logic address is an address which is logically handled by a data processing apparatus (software). A physical address is added to each cluster in the flash memory. A correspondence relation between the clusters and the physical addresses is unchanged.
According to the flash memory, by rewriting data, an insulating film deteriorates and the number of rewriting times is limited. Therefore, it is necessary to prevent a situation that accesses are repetitively and concentratedly performed to a certain same memory area (cluster). In case of rewriting data in a certain logic address stored in a certain physical address, in a file system of the flash memory, updated data is not rewritten into the same cluster but the updated data is written to an unused cluster. Thus, the correspondence relation between the logic addresses and the physical addresses before the data updating changes after the updating. By performing such a swapping process as mentioned above, the situation that the accesses are repetitively and concentratedly performed to the same cluster is prevented, so that a life of the flash memory can be extended.
Since the logic cluster address is accompanied by the data which has once been written into the cluster, even if physical cluster addresses in which the data before updating and the data after the updating are written are changed, the same address is seen from a file management system and the subsequent accesses can be properly performed. Since the correspondence relation between the logic addresses and the physical addresses is changed by the swapping process, a logical/physical address conversion table showing the correspondence between them is needed. By referring to such a table, the physical cluster address corresponding to the designated logic cluster address is specified, thereby enabling the access to the cluster shown by the specified physical cluster address to be performed.
The logical/physical address conversion table is stored in a memory by the data processing apparatus. If a memory capacity of the data processing apparatus is small, the table can be stored in the flash memory.
FIG. 13B
shows an example of a logical/physical address conversion table regarding segment
1
. As shown in
FIG. 13B
, in the logical/physical address conversion table, the physical cluster addresses (2 bytes) are made to correspond to the logic cluster addresses (2 bytes) arranged in the ascending order, respectively. The logical/physical address conversion table is managed every segment and its size increases in accordance with the capacity of the flash memory.
There is a case where it is desirable to set a data writing speed to be higher than the ordinary one by making a plurality of storages of the flash memory operative in parallel. For example, an electronic music distribution EMD for distributing music data through a network is being put into practical use. The distributed music data is stored into a hard disk of a personal computer, data of a desired music piece is copied or moved into a memory card by the personal computer, and the memory card is attached into a portable recorder, so that the user can easily listen to the desired music at a place other than his home. Data of a plurality of music pieces is downloaded into the memory card from the hard disk by a parallel writing operation (at a high speed) and, upon reproduction, the music data is read out from the memory card at a normal speed.
FIG. 14
shows a construction of a conventional logic address for four storages. In he example of the diagram, address spaces in the memory are expressed by 11 bits of A
0
, A
1
, . . . , and A
10
. A
0
denotes the LSB (least significant bit) and A
10
indicates the MSB (most significant bit). The storages each having a capacity of 4 MB are switched by the MSB (A
10
) and the second MSB (A
9
). Addresses of 9 bits of A
0
to A
8
are allocated to a sector and a segment in each storage.
When data is written, the operation is executed at a timing as shown in FIG.
15
. First, the data is transferred from the host side to a page buffer of a sector size. Time T is required to transfer. In a next write busy period, the data is transferred from the page buffer into a flash buffer in the flash memory and the data is written into the storage.
Upon reading, as shown in
FIG. 16
, the data is read out from the flash memory for a read busy period. The read-out data is transferred to a page buffer of a sector size. In the next transfer time T, the data is transferred from the page buffer to the host side.
FIG. 17
is a flowchart showing a flow of processes in case of writing data into continuous logic sectors
0
to
3
belonging to different clusters in a certain segment. In first step S
11
, a logical/physical conversion table is formed with respect to a segment as a target to be written. In step S
12
, sector
0
is sent from the host side. The time T is required for this transfer. In step S
13
, sector
0
is written into the flash memory. In step S
14
, sector
1
is sent from the host side. In step S
15
, sector
1
is written into the flash memory. Processes for sending of sector
2
(step S
16
), writing of sector
2
(step S
17
), sending of sector
3
(step S
18
), and writing of sector
3
(step S
19
) are sequentially performed. Hitherto, for example, even if four storages are provided in parallel, since accesses are concentrated to one storage, a high processing speed cannot be realized.
As for a data construction of one sector on the flash memory, as shown in
FIG. 18
, an area having a length of 16 byte
Araki Shigeo
Nakanishi Kenichi
Frommer & Lawrence & Haug LLP
Le Vu A.
Sony Corporation
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