Recording-medium operating device, clock signal generating...

Details Recording-medium operating device, clock signal generating... Recording-medium operating device, clock signal generating...

2005-03-08

2005-03-08

Young, W. R. (Department: 2651)

Dynamic information storage or retrieval

Control of storage or retrieval operation by a control...

Control of information signal processing channel

C369S053340

Reexamination Certificate

active

06865145

ABSTRACT:
It is intended to provide a recording-medium operating device, a clock signal generating device for the recoding-medium operating device, and a method for generating a clock signal for the recoding-medium operating device that satisfy both operation with a wide-range data transfer rate using delay line provided with not so large number of stages and high correction accuracy and are advantageous in terms of low power consumption and suppression of noises. A reference clock group Ø0through Øx different in phase are obtained by a PLL1. One of the reference clock group is selected by a clock selector2. A selected clock signal is inputted to a delay circuit3and one of output clocks from a delay line31is selected by a selector3. With structure as such, selection by the clock selector2and the selector3is controlled so as to make phase difference between a clock signal and an RF signal minimum. Thereby, time equivalent to phase difference of adjoining two reference clocks is sufficient enough as total delay quantity of the delay line31.

REFERENCES:
patent: 5715222 (1998-02-01), Senshu et al.
patent: 6104682 (2000-08-01), Konishi
patent: 6385150 (2002-05-01), Asano
patent: 20010006500 (2001-07-01), Nakajima et al.
patent: 20020018415 (2002-02-01), Kuroda et al.

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