Recording clock generation circuit

Details Recording clock generation circuit Recording clock generation circuit

2002-08-08

2004-01-06

Nuton, My-Trang (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

Reexamination Certificate

active

06674330

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a recording clock generation circuit for generating a recording clock signal from a wobble signal which is read from an optical disc or the like which is not influenced by crosstalk between adjacent tracks of the optical disc or the like.
2. Description of the Related Art
A conventional recording clock generation circuit will be described with reference to FIG.
4
.
FIG. 4
shows a configuration of a conventional recording clock generation circuit. The conventional recording clock generation circuit includes a first phase comparator
1
for detecting a phase difference between a wobble signal and a PLL (phase-locked loop) internal signal VCOOUT, a first filter
2
for smoothing the output from the first phase comparator
1
, a VCO circuit
3
oscillating in accordance with the smoothed signal, and a frequency divider
4
for dividing the frequency of the output from the VCO (voltage controlled oscillator) circuit
3
. The first phase comparator
1
, the first filter
2
, the VCO circuit
3
and the frequency divider
4
form a PLL.
A wobble signal is read from a physical description on a track of an optical disc or the like and used for generating a recording clock.
An output of the first phase comparator
1
is connected to an input of the first filter
2
. An output of the first filter
2
is connected to an input of the VCO circuit
3
. An output of the VCO circuit
3
is connected to an input of the first phase comparator
1
via the frequency divider
4
.
The conventional recording clock generation circuit shown in
FIG. 4
operates as follows.
A phase difference between an input wobble signal and a PLL internal signal VCOOUT is detected by the first phase comparator
1
and is smoothed by the first filter
2
. The smoothed signal is converted into a signal having a particular frequency by the VCO circuit
3
oscillating in accordance with a value of the input signal. The frequency is input to the first phase comparator
1
via the frequency divider
4
. In other words, a feedback operation is performed such that the phase of the input wobble signal and the phase of the PLL internal signal VCOOUT match each other.
In the case where the frequency divider
4
divides the frequency into N, a recording clock is generated at a particular frequency, which is N times the frequency of the PLL internal signal VCOOUT, so as to be in synchronization with the input wobble signal.
However, the conventional recording clock generation circuit having the above-described structure has a problem in that a correct recording clock (or a recording clock synchronized to the input wobble signal) cannot be generated since the input wobble signal itself is shifted in phase due to interference between adjacent tracks of the disc.
FIG. 5
is a timing diagram illustrating the operation of the conventional recording clock generation circuit shown in FIG.
4
. Section (A) of
FIG. 5
shows a waveform of the wobble signal having a shifted phase due to an influence of crosstalk between adjacent tracks of the disc. When the phase of the wobble signal is shifted as shown in section (A) due to the influence of crosstalk, a recording clock having a shifted phase as shown in section (B) of
FIG. 5
is obtained. Section (C) of
FIG. 5
shows a recording clock obtained in a normal state, i.e., free from any influence of crosstalk. A chain line a represents normal waveforms.
SUMMARY OF THE INVENTION
A recording clock generation circuit according to the present invention includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.
In one embodiment of the invention, the recording clock generation circuit further includes a second filter, provided between the phase adjusting circuit and the second phase comparator, for filtering the phase difference detected by the second phase comparator.
Thus, the invention described herein makes possible the advantages of providing a recording clock generation circuit for generating a recording clock signal which is not influenced by crosstalk.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.


REFERENCES:
patent: 6118742 (2000-09-01), Matsui et al.
patent: 6236629 (2001-05-01), Hisakado et al.
patent: 6489851 (2002-12-01), Miyada et al.
patent: 6542038 (2003-04-01), Nishimura et al.
patent: 6563387 (2003-05-01), Hirano et al.
patent: 2000-067434 (2000-03-01), None

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