Recorded data demodulation circuit

Details Recorded data demodulation circuit Recorded data demodulation circuit

1990-01-02

1991-06-04

Canney, Vincent P.

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

360 32, 360 51, G11B 509, G11B 500

Patent

active

050218948

ABSTRACT:
A clock of a predetermined frequency is generated on a basis of clock information contained in a read signal. Sample values obtained by sampling the read signal in response to the clock are sequentially converted into digital data, and the thus obtained digital data are held in a first data holding means and then second data holding means in response to the clock for a time corresponding to the clock. The digital data and the output data from the second data holding means are added, and the addition output bits are multiplied by a predetermined constant by inserting a selected number of zero bits as upper significant bits, and shifting the addition output bits by the selected number of zero bits. Data corresponding to the difference between the multiplied output and the output of the first data holding means is obtained, and the thus obtained difference output is demodulated in response to the clock.

REFERENCES:
patent: 4675749 (1987-06-01), Banno et al.
patent: 4758903 (1988-07-01), Noguchi et al.

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