Reconstruction of young bits in annex after mispredicted executi

Details Reconstruction of young bits in annex after mispredicted executi Reconstruction of young bits in annex after mispredicted executi

1996-11-20

1998-05-05

Lim, Krisna

395393, 395394, G06F 938

Patent

active

057489351

ABSTRACT:
In a pipelined processor, a method and apparatus for performing restoration of the previous values of young bits in the annex after a mispredicted branch has been detected. In a first embodiment, beginning with the oldest annex entry, the destination register address of that entry is broadcast to all other entries. All annex entries with matching addresses have their young bits reset, while the young bits of the broadcast entry is set. The above broadcast, compare, reset, and set operations are performed on all the remaining valid entries sequentially and in order of decreasing age. When all valid entries have been broadcast, the young bit states are correctly reconstructed. In a second embodiment, each annex entry has a current young bit Y0 and one or more past young bits (Y1 through YN). For branch condition resolutions which take up to N clock cycles, N past young bits are maintained in each annex entry. During every machine cycle in which a new annex entry is received, the contents of Yk is shifted to Yk+1 for all k from 0 to N-1, and the current young bits Y0 are updated. When a mispredicted branch is detected after the results of i speculative instructions have been entered in the annex, the past young bit Yi is restored back into the current young bit Y0 for each annex entry. Thus, restoration of the correct young bits is performed in a small constant time. Both embodiments may be implemented in the same processor to optimize recovery from both short and long latency mispredictions.

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