Reconfigurable transceiver architecture for frequency offset...

Details Reconfigurable transceiver architecture for frequency offset... Reconfigurable transceiver architecture for frequency offset...

2004-12-17

2010-12-07

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Transceivers

C375S220000, C375S222000, C375S297000, C375S327000, C375S342000, C331S002000, C331S016000, C327S101000, C327S144000

Reexamination Certificate

active

07848394

ABSTRACT:
A first serial transceiver has a reference clock, a first transmitter, and a first receiver. The first receiver includes (i) a phase detector, and (ii) a phase rotator. The phase rotator is driven by the reference clock. A first multiplexer is coupled to the first receiver. The first multiplexer receives the phase detector output and a control signal. When the first serial transceiver is in a test configuration, the first multiplexer passes the control signal to the phase rotator, thereby varying the frequency of the phase rotator output. A second multiplexer is coupled to the first transmitter. The second multiplexer receives a reference clock signal and the phase rotator output. When the first serial transceiver is in a test configuration, the second multiplexer passes the phase rotator output to the first transmitter. The first transmitter thereby transmits a serial data stream that varies in frequency from said reference clock.

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