Reconfigurable programmable logic device

Details Reconfigurable programmable logic device Reconfigurable programmable logic device

1995-05-31

1996-08-20

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

326 38, G11C 1134

Patent

active

055485529

ABSTRACT:
The present invention provides a reconfigurable programmable logic device (PLD) that saves its own programmed state without the use of an external memory device or without additional control logic on the PLD. A non-volatile memory cell is incorporated with each SRAM cell in the PLD to form a configuration memory cell. The non-volatile memory cells store the programmed states of the associated SRAM cells even after termination of power to the system. Each non-volatile memory cell then restores the configured state of its associated SRAM cell upon system power-up by "mapping" its contents to the SRAM cell. The non-volatile memory cell may be implemented either by an Erasable Programmable Read Only Memory cell ("EPROM") or an Electrically Erasable Programmable Read Only Memory cell ("EEPROM").

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"iFX740 10 ns FLEXlogic FPGA with SRAM Option," Intel Corporation product bulletin, Nov. 1993.

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