Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-09-23
2001-10-30
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C326S039000
Reexamination Certificate
active
06311200
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to reconfigurable logic chips.
Reconfigurable logic chips, such as field programmable gate arrays (FPGAs) have become increasingly popular. Such chips allow logic to implement different circuits at different times.
FPGAs are being increasingly used because they offer greater flexibility and shorter development cycles than traditional Application Specific Integrated Circuits (ASICs) while providing most of the performance advantages of a dedicated hardware solution.
One growingly popular use of FPGAs is referred to as reconfigurable computing. In reconfigurable computing, hardware logic functions are loaded into the FPGA as needed to implement different sections of a computationally intensive code. By using the FPGAs to do the computational intensive code, advantages are obtained over dedicated processors. Reconfigurable computing is being pursued by university researchers as well as FPGA companies.
Many FPGAs implement logic using lookup tables with feedback. These systems tend to be slow and inefficient especially for reconfigurable computing uses. It is desired to have an improved reconfigurable chip for reconfigurable computing.
SUMMARY OF THE PRESENT INVENTION
The present invention comprises a reconfigurable programmable sum of products (PSOP) generator. The reconfigurable programmable sum of products generator of the present invention is reconfigurable for a number of different functions using a configuration memory.
In a preferred embodiment, multiple configuration planes are stored local to the reconfigurable programmable sum of products generator. This allows the reconfigurable programmable sum of products generator to switch between the different configuration planes without waiting for the loading of a configuration from off-chip. In one embodiment, the configuration memory for the reconfigurable sum of products generator uses master/slave latches. Preferably, a backup configuration plane can be loaded from off-chip, while a foreground configuration plane is connected to the reconfigurable PSOP generator. This speeds the operation of the reconfigurable chip.
The memory units for the reconfigurable PSOP generator are preferably interspersed with the other elements of the reconfigurable PSOP generator. The memory units can be loaded using configuration lines. In a preferred embodiment, a relatively large number of configuration bits are loaded during each cycle to increase the configuration loading speed.
Conventional prior art PLAs are typically one-time programmable by designing a metalization layer to connect or not connect transistors in the PLA. Other prior art devices include Programable Array Logic© (PAL©), which connects AND and OR planes using fusible links, UV-erasable EPROM link or E
2
ROM links. Such PALs tend to take a significant amount of time to program and thus are typically used for static designs and are inappropriate for use in a reconfigurable computing environment. Additionally, such connections do not allow for using multiple configuration planes.
In a preferred embodiment of the present invention, the reconfigurable programmable sum of products generator is arranged as a reconfigurable dynamic PSOP generator. Dynamic programmable sum of products generators use precharged product term lines and output lines. In a preferred embodiment of the present invention, the programmable sum of products generator is arranged so that the precharging of the product term and output lines is done during a first portion of the cycle, and the evaluation of the product plane and summation plane is done in the second portion of the cycle. This produces speed advantages for the entire circuit because the first part of the cycle can be used by other circuitry to produce the inputs to the reconfigurable programmable sum of products generator. Power consumption is also reduced. Conventional dynamic programmable sum of products generators precharge a first plane and evaluate a second plane during one half-cycle, and precharge the second plane and evaluate the first plane during the other half-cycle.
The reconfigurable programmable sum of products generator structure of the present invention is dense and highly interconnected and thus is advantageous for the control fabric of a reconfigurable chip. In one embodiment, the reconfigurable programmable sum of products generator is arranged as a state machine so as to produce addresses to a configuration state memory. The configuration state memory uses these addresses to provide configuration bits for a data path unit. The configuration state memory unit can be arranged so that a relatively few address bits can output a relatively large number of data path unit configuration bits.
REFERENCES:
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4831285 (1989-05-01), Gaiser
patent: 4876466 (1989-10-01), Kondou et al.
patent: 4972105 (1990-11-01), Burton et al.
Hanrahan Shaila
Phillips Christopher E.
Burns Doane , Swecker, Mathis LLP
Chameleon Systems, Inc.
Malzahn David H.
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