Reconfigurable, multi-user Viterbi decoder

Details Reconfigurable, multi-user Viterbi decoder Reconfigurable, multi-user Viterbi decoder

1990-09-27

1992-09-29

Beausoliel, Robert W.

Excavating

371 41, G06F 1110

Patent

active

051519046

ABSTRACT:
A decoding system for decoding a digital data stream that has been convolutionally encoded in accordance with a selected constraint length and selected polynomial codes, which system includes a processor, such as a Viterbi decoder, that is reconfigurable so that it can decode encoded digital data streams for a number of different user channels for which data streams have been convolutionally encoded in accordance with respectively different combinations of selected constraint length and selected polynomial codes. The decoding system includes a Viterbi decoder for processing the encoded data stream in accordance with said selected constraint length and in accordance with said selected polynomial codes to decode the encoded data stream; a RAM for storing data of said selected constraint length and data of said selected polynomial codes in accordance with which said data stream was encoded; and a RAM I/O interface circuit responsive to a user channel identification signal for retrieving said selected constraint length data and said selected polynomial code data from the RAM and configuring the Viterbi decoder in accordance with said selected constraint length and said selected polynomial codes. In order to accommodate concurrent multiple user channels, the RAM stores different sets of combinations of constraint length data and polynomial code data corresponding to different user channels, with said different sets being retrievable from the RAM in response to respectively different user channel identification signals. The polynomial code data and constraint length data in the RAM may be changed from time to time in response to software instructions, as user channel requirements change. The Viterbi decoder processes said encoded data stream over a plurality of decoding cycles and produces intermediate decoding results during different decoding cycles; and the RAM I/O interface circuit stores in the RAM said intermediate decoding results produced for each different user channel during the different decoding cycles.

REFERENCES:
patent: 3078443 (1963-02-01), Rose
patent: 4583236 (1986-04-01), Kromer
patent: 4701923 (1987-10-01), Fukashawa
patent: 4805174 (1989-02-01), Kubota
Viterbi, "Error Bounds for Convolutional Codes and an Asymptotically Optimum Recording Algorithm", IEEE Transactions on Information Theory, vol. IT-13, No. 2, Apr. 1967, pp. 260-269.
Odenwalder, "Error Control", Data Communications, Networks and Systems, Bartee, Ed. Sams 1985, Ch. 10, pp. 289-354.
Yasuda et al., "Development of Variable-Rate Viterbi Decoder and Its Performance Characteristics", Sixth International Conference on Digital Satellite Communications, Sep. 19-23, 1983, pp. XII-24 to XII-31.

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