Boots – shoes – and leggings
Patent
1979-07-02
1981-10-06
Shaw, Gareth D.
Boots, shoes, and leggings
G11C 700, G08B 2900
Patent
active
042939100
ABSTRACT:
The disclosure provides a storage protection (SP) array in each of two system controllers (SCs) in a multiprocessing system which has a shared main storage containing a plurality of basic storage modules (BSMs). The BSMs may be operated with block and page interleaved addresses. Each block in main storage is assigned a key-in-storage having an entry in one of the two arrays.
A cross-interrogate (XI) bus connects between the SCs. Using the XI bus, each processor request is sent to an SP address register in every SP array.
Each array is divided into a plurality of equal groups. Each group has a range identifier register and a comparator. The range identifier register is loaded with a value which controls the range of main storage addresses to which the group is assigned. All of the comparators in each array are connected to a high-order part of the SP address register for the array.
The range identifier registers in all of the groups in both arrays are assigned different values which cover the entire address range of main storage, and only one array need contain a particular key-in-storage. A BSM bit and a page bit in the processor request address are put into the high-order field of the SP address register to control the selection of a group, so that alternate pages have their keys-in-storage put in different groups in a pair of groups in a SP array.
Key-in-storage accesses may be overlapped between different groups in an array.
When a request received from the XI bus has its key-in-storage found in one array, the key-in-storage is transmitted on the XI bus to the SC which sent the request.
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Flusche Frederick O.
Tan Kwang G.
Wright Ralph W.
Chan Eddie P.
Goldman Bernard M.
International Business Machines - Corporation
Shaw Gareth D.
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