Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2007-06-30
2010-02-09
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C710S317000
Reexamination Certificate
active
07660968
ABSTRACT:
A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.
REFERENCES:
patent: 3783192 (1974-01-01), Takahashi
patent: 3984819 (1976-10-01), Anderson
patent: 4380065 (1983-04-01), Hirtle et al.
patent: 4597077 (1986-06-01), Nelson et al.
patent: 4663620 (1987-05-01), Paul et al.
patent: 4799260 (1989-01-01), Mandell et al.
patent: 4807183 (1989-02-01), Kung et al.
patent: 4928260 (1990-05-01), Chuang et al.
patent: 4963768 (1990-10-01), Agrawal et al.
patent: 4996530 (1991-02-01), Hilton
patent: 5028821 (1991-07-01), Kaplinsky
patent: 5036300 (1991-07-01), Nicolai
patent: 5046098 (1991-09-01), Mandell et al.
patent: 5107146 (1992-04-01), El-Ayat
patent: 5153462 (1992-10-01), Agrawal et al.
patent: 5227863 (1993-07-01), Bilbrey et al.
patent: 5261059 (1993-11-01), Hedberg et al.
patent: 5392446 (1995-02-01), Tower et al.
patent: 5428750 (1995-06-01), Hsieh et al.
patent: 5444705 (1995-08-01), Olnowich et al.
patent: 5481471 (1996-01-01), Naglestad et al.
patent: 5511222 (1996-04-01), Shiba et al.
patent: 5555397 (1996-09-01), Sasama et al.
patent: 5555543 (1996-09-01), Grohoski et al.
patent: 5559971 (1996-09-01), Hsieh et al.
patent: 5603061 (1997-02-01), Hilley et al.
patent: 5610545 (1997-03-01), Jenkins et al.
patent: 5732207 (1998-03-01), Allen et al.
patent: 5751234 (1998-05-01), Schlotterer et al.
patent: 5764080 (1998-06-01), Huang et al.
patent: 5796312 (1998-08-01), Hull et al.
patent: 5821776 (1998-10-01), McGowan
patent: 5822610 (1998-10-01), Fung et al.
patent: 5847450 (1998-12-01), Fink et al.
patent: 5861681 (1999-01-01), Nakano et al.
patent: 5861829 (1999-01-01), Sutardja
patent: 5880690 (1999-03-01), Rothenberg
patent: 5949982 (1999-09-01), Frankeny et al.
patent: 6037891 (2000-03-01), Griph
patent: 6232907 (2001-05-01), Nagaraj et al.
patent: 6262594 (2001-07-01), Cheung et al.
patent: 6263415 (2001-07-01), Venkitakrishnan
patent: 6289494 (2001-09-01), Sample et al.
patent: 6351231 (2002-02-01), Price et al.
patent: 6367032 (2002-04-01), Kasahara
patent: RE37716 (2002-05-01), Sutardja et al.
patent: 6420990 (2002-07-01), Voelkel
patent: 6490213 (2002-12-01), Mu et al.
patent: 6496880 (2002-12-01), Ma et al.
patent: 6507581 (2003-01-01), Sgammato
patent: 6643803 (2003-11-01), Swoboda et al.
patent: 6662314 (2003-12-01), Iwata et al.
patent: 6803785 (2004-10-01), May et al.
Hashimoto, Masashi; self-Routing Optical Crossbar Switch; IEEE Photonics Technology Letters, vol. 2, No. 7, Jul. 1990, pp. 522-524.
“MicroConverter, Multichannel 12-Bit ADC with Embedded Flash MCU”, Analog Devices, 2003, pp. 1-60, Norwood MA.
Computer System Architecture; Second Edition; M. Morris Mano; 1982 by Prentice Hall, Inc. pp. 454-458.
On the Speedup Required for Work-Conserving Crossbar Switches; Krishna et al.; IEEE Journal on Selected Areas in Communications, vol. 17, No. 6, Jun. 1999; pp. 1057-1066.
Testing Crossbar Switch Interconnection Networks; Janusz Sosnowski, Institute of Computer Science, Warsaw University of Technology; ul. Nowowiejska 15/19; Warsaw 00-665, Poland.
Alfano Donald E.
Allred Danny J.
Caloway Brian
Fernald Kenneth W.
Highley Paul
Howison & Arnott , L.L.P.
Kim Kenneth S
Silicon Labs CP Inc.
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