Reconfigurable integrated circuit with enhanced testability of m

Details Reconfigurable integrated circuit with enhanced testability of m Reconfigurable integrated circuit with enhanced testability of m

1986-12-05

1989-01-24

Karlsen, Ernest F.

Electricity: measuring and testing

Plural, automatically sequential tests

365201, 371 21, G01R 3128, G11C 700

Patent

active

048003328

ABSTRACT:
A memory device is described which has the capability for testing portions of its circuitry with a variable test voltage, while allowing the remainder of the circuit to not be affected by variations in the test voltage. A specific example of a test utilizing this feature is a test directed to the leakage of stored charge in a dynamic memory cell through its access transistors controlled by the row lines. A circuit is disclosed which connects a test voltage terminal through a first fuse to the node to which the row decoder biases the unselected row lines. A second fuse and associated circuitry decouples the normal reference supply from this particular node, but does not affect the presence of the reference supply elsewhere in the memory device. The voltage of the test voltage terminal may be modulated to determine the voltage at which the access transistors in the array cause stored charge to leak during a memory cycle which selects another row in the array. After testing is completed, the fuses may be opened by way of a laser beam, thereby connecting the reference supply to the node for biasing unselected row lines, for normal operation.

REFERENCES:
patent: 3242428 (1966-03-01), Brumley et al.
patent: 4494066 (1985-01-01), Goel et al.

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