Reconfigurable high-performance texture pipeline with...

Details Reconfigurable high-performance texture pipeline with... Reconfigurable high-performance texture pipeline with...

2011-02-08

2011-02-08

Wesner, Sajous (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics processing

Attributes

C345S428000, C345S587000, C345S606000, C345S552000, C382S254000, C382S260000, C382S300000, C382S303000, C711S100000, C711S113000, C711S123000, C711S127000

Reexamination Certificate

active

07884831

ABSTRACT:
Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

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U.S. Appl. No. 11/960,645, filed Dec. 19, 2007.

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