Pulse or digital communications – Equalizers
Reexamination Certificate
2007-10-02
2007-10-02
Ghayour, Mohammed (Department: 2611)
Pulse or digital communications
Equalizers
C708S300000, C708S301000, C708S316000
Reexamination Certificate
active
10248920
ABSTRACT:
A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer has inputs connected to the input node and to an output of the register, an output of the multiplexer for connecting to a next stage DPU. The coefficient multiplier is connected to the output of the register and multiplies the input signal by a coefficient or part of a coefficient. A group of DPUs can have multiplexers set so that the register of each DPU stores the same part of the input signal for processing a single filter coefficient. An adder is provided to sum output of the DPUs and output a filtered signal. The critical path of the FIR filter is independent of coefficient number and precision.
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Chen Kuan-Hung
Chiueh Tzi-Dar
Ghayour Mohammed
Hsu Winston
Mediatek Inc.
National Taiwan University
Vlahos Sophia
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