Reconfigurable data path processor

Details Reconfigurable data path processor Reconfigurable data path processor

2005-04-19

2005-04-19

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

C712S011000, C712S015000, C712S016000

Reexamination Certificate

active

06883084

ABSTRACT:
A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.

REFERENCES:
patent: 4839851 (1989-06-01), Maki
Donohoe et al., “Reconfigurable Data Path Processor for Space”, Proceedings of the Military and Aerospace Applications of Programmable Logic Devices 2000, Laurel, MD, Sep. 24-28, 2000.*
Donohoe et al., “Adaptive Computing for Space”, 42nd Midwest Symposium on Circuits and Systems, Aug. 8-11, 1999, vol. 1, pp. 126-129, IEEE.*
Seth Copen Goldstein et al., “PipeRench: A Reconfigurable Architecture and Complier,” Apr. 2000 pp. 70-77.
Masakatsu Maruyama et al., “An Image Signal Multiprocessor on a Single Chip,” IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1476-1483.

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