Reconfigurable computing based multi-standard video codec

Details Reconfigurable computing based multi-standard video codec Reconfigurable computing based multi-standard video codec

2007-06-26

2007-06-26

Philippe, Gims (Department: 2621)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240250

Reexamination Certificate

active

10443973

ABSTRACT:
A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be configured to (i) load the first program directly from the multiported memory to program a codec function and (ii) generate a video output signal by performing the codec function on a video input signal using video data exchanged with the multiport memory.

REFERENCES:
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5784636 (1998-07-01), Rupp
patent: 6275891 (2001-08-01), Dao et al.
patent: 2003/0222144 (2003-12-01), Meier et al.

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