Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-05-31
2011-05-31
Petranek, Jacob (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S010000
Reexamination Certificate
active
07953956
ABSTRACT:
A reconfigurable circuit of reduced circuit scale. The reconfigurable circuit of the present invention comprises a plurality of ALUs capable of changing functions. The plurality of ALUs are arranged in a matrix. At least one connection unit capable of establishing connection between the ALUs selectively is provided between the stages of the ALUs. This connection unit is not intended to allow connection between all the logic circuits in adjoining stages, but is configured so that the logic circuits are each connectable with only some of the logic circuits pertaining to the other stages. The connection limitation allows a reduction in circuit scale.
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Hiramatsu Tatsuo
Nakajima Hiroshi
Okada Makoto
Ozone Makoto
McDermott Will & Emery LLP
Petranek Jacob
Sanyo Electric Co,. Ltd.
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