Metal working – Method of mechanical manufacture – Electrical device making
Patent
1997-11-17
1999-08-17
Vo, Peter
Metal working
Method of mechanical manufacture
Electrical device making
29830, 29831, 29832, 29850, 29884, H05K 332, H05K 336, H05K 346
Patent
active
059375159
ABSTRACT:
A method of manufacturing electronic circuitry and the resulting hardware is described in which a conduction plate is formed achieving separate electrical conducting paths for application specific signals is engaged with an electronic circuit package containing a wide range of elements including one or more integrated circuits, chip packages, multichip modules printed circuit boards and cables. One or more of these elements are assembled into the circuit package where all or a major portion of the element conductors are routed to terminals positioned for electrical connection between the circuit apparatus and the electrical conduction plate. The conduction plate completes the electrical interconnection of the circuit package by providing the application specific conduction paths, using various techniques for creating electrical conduction, such as severing segments of a generalized conductive grid to establish desired conduction paths. The conduction plate, being separate and separable from the circuit package, enables separate design, manufacture, testing and repair of the circuit package and the conduction plate before or following final assembly of the conduction plate and circuit package. Intermediate conduction plate structures may be used to test the devices and the circuit package before final assembly, and the operational conduction plate customized to avoid defects located in the test procedure. Very substantially increased size and capacity of computers and related devices can be achieved in the same or smaller footprint using this invention.
REFERENCES:
patent: 4234888 (1980-11-01), Calhoun et al.
patent: 4597617 (1986-07-01), Enochs
patent: 4628406 (1986-12-01), Smith et al.
patent: 4647959 (1987-03-01), Smith
patent: 4652974 (1987-03-01), Rayan
patent: 4685033 (1987-08-01), Inoue
patent: 4700214 (1987-10-01), Johnson
patent: 4720470 (1988-01-01), Johnson
patent: 4720915 (1988-01-01), Kennedy et al.
patent: 4736521 (1988-04-01), Dohya
patent: 4891585 (1990-01-01), Janko et al.
patent: 5048178 (1991-09-01), Bindra et al.
patent: 5055907 (1991-10-01), Jacobs
patent: 5109555 (1992-05-01), Sample et al.
patent: 5155905 (1992-10-01), Miller, Jr.
patent: 5165166 (1992-11-01), Carey
patent: 5199165 (1993-04-01), Crawford et al.
patent: 5237743 (1993-08-01), Bucsacco et al.
patent: 5329695 (1994-07-01), Traskos et al.
patent: 5497545 (1996-03-01), Watanabe et al.
patent: 5509203 (1996-04-01), Yamashita
"Aptix Programmable Interconnect Brochure", Date Unknown.
"Aptix takes radical approach to pcbs, Electronic Engineering Times, Apr. 27, 1992, p. 94".
"Systems Ees see future in 3-D, Electronic Engineering time, Sep. 24, 1990, p. 37".
"Harwin Chiprack (TM) Brochure" Harwin, Inc., New Albany, In. Date Unknown.
"Demountable TAB Aids Rework and Repair, Connection Technology, Dec. 1991, pp. 26-30".
"CPLD Module Packs 50K Usable Gates, 360 I/O Pins, Electronic Design, Apr. 4, 1994, pp. 45-48".
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