Reconfigurable cache memory which can selectively inhibit access

Details Reconfigurable cache memory which can selectively inhibit access Reconfigurable cache memory which can selectively inhibit access

1992-09-23

1995-04-25

Robertson, David L.

395400, G06F 1314

Patent

active

054106680

ABSTRACT:
A cache memory system includes a buffer having a plurality of segments storing lines of data in addressable storage locations. A first access path is used for accessing the plurality of segments in parallel for access by the CPU, and a second access path is provided for access to the plurality of segments in the buffer in parallel for cache consistency access. Access to damaged segments is selectively disabled by inhibiting tag match and line replacement through the first access path without affecting the second access path. Thus, by disabling the first access path to selected segments, a damaged segment is reconfigured offline without a quiescent state or an extended clocks off period affecting CPU performance.

REFERENCES:
patent: 4912632 (1990-03-01), Gach et al.
patent: 5161162 (1992-11-01), Watkins

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