Recognizing muliplexers

Details Recognizing muliplexers Recognizing muliplexers

2011-05-17

2011-05-17

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S132000, C716S135000

Reexamination Certificate

active

07945877

ABSTRACT:
A chain of multiplexers disposed in a logic block is recognized as a selector and a group of logic gates disposed in the logic block and supplying signals to the select pins of the selector is recognized as a decoder, the selector and the decoder together define a n:1 multiplexer. To achieve this, a group of logic gates supplying signals to the select pins of the selector is identified within the logic block. A truth table defining the logic relationship between the signals applied to the group of logic gates and data signals received by the chain of muxes is generated. The chain of muxes is replaced with a selector upon determination that the rows in the truth table are disjoint. After replacing the chain of muxes with a selector, the process is repeated in a similar manner to replace the remaining logic blocks with a decoder.

REFERENCES:
patent: 6151568 (2000-11-01), Allen et al.
patent: 6505337 (2003-01-01), Wittig et al.
patent: 6519755 (2003-02-01), Anderson
patent: 6526563 (2003-02-01), Baxter
patent: 7428722 (2008-09-01), Sunkavalli et al.
patent: 7735045 (2010-06-01), Van Mau et al.
patent: 2008/0129334 (2008-06-01), Sunkavalli et al.

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