Reclocker circuit and router cell

Details Reclocker circuit and router cell Reclocker circuit and router cell

2000-10-17

2004-09-14

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S419000, C370S359000, C327S407000, C327S365000, C379S290000

Reexamination Certificate

active

06791977

ABSTRACT:

BACKGROUND
1. Technical Field
This patent application is directed to the field of signal switching and routing. More specifically, the application describes an improved reclocker circuit and router cell that are particularly useful in switching and routing video, telecommunication, or other types of time-sensitive signals in a large router matrix comprising a plurality of interconnected router cells.
2. Description of the Related Art
The core building block of the modern television studio is the video router. The video router is a switch matrix that is coupled to and routes signals between numerous video sources and numerous processing devices within the studio. Because timing is an important aspect of routing and processing video signals (as well as other types of signals), video routers typically employ reclocking circuitry in order to correct the timing of the numerous signals that are routed through the matrix. Typical video routers in use today may have 40 or more inputs and outputs and are typically configured as a matrix of interconnected router cells.
When signals pass through a router, or through any other type of communication circuitry, the signals typically experience timing jitter. This timing jitter is manifested as a variation in the period of a signal waveform that typically cannot be removed by amplification and clipping, even if the signal is binary. As a result, systems for switching and/or processing time-sensitive signals typically employ a phase-locked loop (PLL) to extract a jitter-free version of a clock signal, which is then used to synchronize the signal being routed or processed. This extraction and synchronization process is generally referred to in this field as “retiming” or “reclocking,” and devices that perform this process are typically referred to as “retimers” or “reclockers.” Another commonly-used term for this device is a “data regenerator.” A typical retiming (reclocking) circuit is the Gennum GS9035, available from Gennum Corp. of Burlington, Ontario.
Typical reclocker circuits, however, cannot perfectly correct the timing of the input signal, and thus there is still some small amount of jitter that remains in the signal. This remaining jitter creates a problem for video routers having a large number of router cells (and hence a large number of sequential reclocker circuits), because the small amount of jitter that remains in the signal being routed is additive from router cell to router cell. Eventually this additional jitter builds up to a point at which the data content of the signal has been degraded so as to become unusable.
FIG. 1
is a block diagram of a known router cell
10
. This router cell
10
includes an input (A)
18
, an output (Y)
20
, an equalizer
12
, a switch
14
, and a reclocker circuit
16
. The input signal (A)
18
is typically coupled to the equalizer
12
prior to being switched, in order to compensate for studio cable or other lossy medium over which the signal is transmitted. The output of the equalizer
12
is then coupled to the input of the switch
14
. The switch
14
either connects or disconnects the input signal (A)
18
to the output (Y)
20
. Prior to outputting the signal (Y), however, the signal is processed by a reclocker circuit
16
. The reclocker circuit
16
retimes the data in the input signal (A)
18
before transmitting it to subsequent router cells, or outside of the router matrix to some device in the studio. This retiming function is necessary in practical signal switching systems in order to ensure the timing integrity of the data within the signals being switched through the router. The router cell
10
shown in
FIG. 1
is considered non-expandable, as the maximum number of inputs is limited to one (A)
18
.
FIG. 2
is a block diagram of a known router cell
10
with a single expansion input/output pair router (Xi, Xo)
22
,
24
. The router cell
10
shown in
FIG. 2
includes many of the same elements as the cell shown in FIG.
1
. In
FIG. 2
, however, an expansion input/output pair (Xi, Xo)
22
,
24
, a 2-to-1 (2:1) multiplexer
26
, and a second reclocker circuit
16
have been added to the router cell. These additional elements enable the router cell
10
to be expandable so as to form a matrix of router cells, as further shown below with reference to FIG.
4
.
In this router cell
10
, the expansion input (Xi)
22
and the output of the switch
14
are routed to a 2:1 multiplexer
26
. The 2:1 multiplexer
26
selects one of the inputs (Xi)
22
or (A)
18
for routing to the first reclocker circuit
16
and then onto the router cell output (Y)
20
. The input signal (A)
18
is routed through the switch
14
and is then coupled to the second reclocker circuit
16
before being output on the expansion output line (Xo)
24
.
FIG. 3
is a simplified schematic of the router cell shown in FIG.
2
.
FIG. 4
is a schematic of a known router matrix comprising a plurality of router cells. Using the router cell
10
shown in
FIG. 2
as a basic building block, a router matrix can be created by connecting one router cell to one or more other cells. For example, as shown in
FIG. 4
, a four input, four output router matrix can be constructed using
16
router cells
10
. The router cells
10
are organized into a two-dimensional matrix structure comprising a plurality of rows and columns. The signal inputs A
0
, A
1
, A
2
and A
3
(
18
) are coupled to the first row of router cells
10
located at the top of the router matrix. The expansion inputs Xi
0
, Xi
1
, Xi
2
, and Xi
3
(
22
) are coupled to the first column of router cells
10
located on the left side of the matrix. The signal outputs Y
0
, Y
1
, Y
2
and Y
3
(
20
) are coupled to the last column of router cells
10
located on the right side of the matrix. And the expansion outputs Xo
1
, Xo
2
, Xo
3
, and Xo
4
(
24
) are coupled to the last row of router cells
10
located at the bottom of the router matrix. The remaining cells in the matrix are then configured as shown in
FIG. 4
in order to connect the inputs
18
,
22
to the outputs
20
,
24
.
In the router shown in
FIG. 4
, connecting signal input A
0
to output Y
3
produces a path that reclocks the input data signal seven times. To get from A
0
to Y
3
, the signal at A
0
is routed through router cells
10
A,
10
B,
10
C,
10
D,
10
E,
10
F, and
10
G (i.e., seven router cells). It can be seen from this architecture that the longest path through an N×N router designed in this manner results in the input signal being reclocked 2N−1 times. Thus, for the 4×4 matrix shown in
FIG. 4
, the number of reclocks is 2(4)−1 or 7.
The disadvantage with this router design is that the number of reclocks in the longest path expands linearly with the size of the router. With jitter accumulating from each reclocker circuit, every subsequent stage in the matrix will encounter more difficulty in retiming the data. Eventually, the additive jitter induced in the data signal will be such that the reclocker circuit
16
cannot retime the signal being routed through the matrix, at which point the signal is relatively useless.
SUMMARY
An improved reclocker circuit and router cell are provided that are particularly useful when configured into a router matrix comprising a plurality of interconnected router cells. The improved reclocker circuit includes an integral N-to-1 multiplexer (MUX), wherein N is at least three. The improved router cell includes the reclocker/MUX circuit, a switch, and a fan-out circuit. A plurality of ports are coupled to the router cell circuitry, including an input port, an output port, a plurality of expansion input ports, and a plurality of expansion output ports. The improved router cell couples either the input port or one the expansion input ports to its output port, and it also couples the input port to each of the expansion output ports. By using the improved router cells in the design of a router matrix, jitter induced by the reclocker circuits is minimized.
According to one aspect of the invention, a router matrix is provided

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