Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2002-10-01
2004-01-27
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S146000, C257S163000, C257S170000
Reexamination Certificate
active
06683330
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to semiconductor devices and, more specifically, to thyristor-based semiconductor devices, such as thyristor-based memory devices and other thyristor-based current-switching circuits.
Background
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F
2
and 8 F
2
, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F
2
and 100 F
2
.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for thyristor-based applications. An important consideration in the design of the thin capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Another important consideration in semiconductor device design and manufacture, including the design and manufacture of devices employing thin capacitively coupled thyristor-type devices and memory circuits, includes manufacturing the device without changing the structure of or otherwise damaging the device. For example, when circuit regions are ion implanted, adjacent circuit regions can sometimes be undesirably implanted and, in some instances, this undesirable implantation can damage the device being manufactured. For instance, dielectric materials, such as those employed between gate electrodes and channel regions, are susceptible to ion implant damage.
These and other design considerations have presented challenges to efforts to implement such a thin capacitively-coupled thyristor in bulk substrate applications, and in particular to applications susceptible to ion implant damage.
SUMMARY
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in other circuits, such as memory circuits. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device includes a thyristor having a control port and a body region in a substrate, the control port being separated from the body region by a dielectric material. The control port is recessed from a dopable region of the substrate, such that ion-implantation of the dopable region does not implant the dielectric material between the control port and the body region. With this approach, challenges to the manufacture and implementation of semiconductor devices, including those discussed above, are addressed.
In one specific example approach, a trench is etched in a semiconductor substrate that has at least one region of a thyristor and a dopable region therein. A dielectric material is formed on a sidewall of the trench facing the at least one thyristor region, and a control port is formed in the trench and recessed below the dopable region, relative to an upper surface of the substrate. The control port is adapted for capacitively coupling to the thyristor region via the dielectric material for controlling current flow in the thyristor. Filler material is formed in the trench and over the control port. The dopable region is subsequently implanted while using material above the control port and in the substrate, such as the filler material and/or portions of the thyristor, to inhibit the implantation of a portion of the dielectric material (e.g., via which the thyristor is adapted for capacitively coupling).
In another example embodiment of the present invention, a semiconductor device includes a thyristor and a substrate having an upper surface. The thyristor includes a control port and at least one body region that is in the substrate. The control port is in a filled trench that is adjacent to the thyristor body region and includes a dielectric material on a portion of a sidewall thereof. The control port has an uppermost portion recessed below the upper surface of the substrate and is adapted for capacitively coupling to the thyristor body region in the substrate via a portion of the dielectric material extending alongside the control port and below the uppermost portion. A region of the substrate adjacent to the upper surface includes a species of ions implanted therein, wherein the dielectric material portion extending alongside the control port and below the uppermost portion of the control port does not include the species of ions.
In a more particular implementation, the control port is adapted for capacitively coupling at least one voltage transition to the at least one thyristor region in the substrate. The capacitive coupling causes an outflow of minority carriers from the at least one thyristor region and switches the thyristor at least from a current-passing mode to a current-blocking mode for current flow in the thyristor body.
In another exam
Horch Andrew
Robins Scott
Ngo Ngan V.
T-Ram, Inc.
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