Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1999-02-19
1999-11-09
Jackson, Jr., Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257510, 257515, 257374, 257754, H01L 29772, H01L 310352, H01L 27105
Patent
active
059820179
ABSTRACT:
A shallow trench isolated FET LDD structure that has a low probability of short circuiting at the silicon to trench interface or between the source or drain and the gate (because of a titanium silicide bridge) is described. It is based on an isolation trench having a top portion with vertical sides and a lower portion with sloping sides. With the filled trench in place, along with a polysilicon gate and gate oxide, the thinner, lightly doped, N type layer is formed using ion implantation. Spacers are then formed on the gate but, prior to the second ion implant step, a few hundred Angstroms of silicon is selectively removed from the surface. This causes the trench filler material to extend above the wafer surface and the spacers to extend above the gate. A deeper, more strongly N-type, layer is then formed in the usual way, followed by the standard SALICIDE process for making contact to source, gate, and drain.
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Liu Jing-Meng
Tsai Chao-Chieh
Wu Sheng-Jyh
Ackerman Stephen B.
Jackson, Jr. Jerome
Saile George O.
Taiwan Semiconductor Manufacturing Company
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