Recessed sidewall-sealed and sandwiched poly-buffered LOCOS isol

Details Recessed sidewall-sealed and sandwiched poly-buffered LOCOS isol Recessed sidewall-sealed and sandwiched poly-buffered LOCOS isol

1995-06-07

1997-03-04

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257649, H01L 2900

Patent

active

056082568

ABSTRACT:
This is a method for forming a recessed LOCOS isolation region, which includes the steps of forming a first silicon nitride layer between the pad oxide layer and a polysilicon buffer layer and a second nitride layer over the polysilicon buffer layer. In addition, the method for forming LOCOS isolation regions can include the additional steps of forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation regions have provided a low-profile recessed field oxide with reduced oxide encroachment into the active moat region.

REFERENCES:
patent: 5159428 (1992-10-01), Rao et al.
patent: 5294563 (1994-03-01), Rao
patent: 5298451 (1994-03-01), Rao
patent: 5410176 (1995-04-01), Liou et al.

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