Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Patent
1994-03-03
1996-08-20
Loke, Steven H.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
257280, 257282, 257283, H01L 2980, H01L 31112
Patent
active
055481442
ABSTRACT:
A high power output semiconductor device having a plurality of FET elements on a semi-insulating semiconductor substrate including a first conductivity type semiconductor layer on the semi-insulating semiconductor substrate, a plurality of source and drain electrodes alternatingly arranged on the semiconductor layer, a plurality of gate electrodes respectively disposed in gate recesses formed by etching respective surface regions of the semiconductor layer between each adjacent source and drain electrodes. The gate recess has a asymmetrical two-stage recess structure having a second bottom surface only at the source side of the recess at a depth between a first bottom surface in contact with the gate electrode and the upper surface of the semiconductor layer and is not in contact with the gate electrode. Therefore, the thickness of the active layer at the source side is increased as compared with that in the one-stage recess structure, with the result that the source resistance is reduced because of an increase in the thickness of the active layer at the source side region while avoiding deterioration of the gate drain breakdown voltage due to an increase in the thickness of the active layer at the drain side region.
REFERENCES:
patent: 4939557 (1990-07-01), Pao et al.
Proceedings of the 11th Conference (1979 International) on Solid State Devices, Tokyo 1979, Japanese Journal of Applied Physics, vol. 19 (1980) Supplement 19-1, pp. 339-343, "Power GaAs MESFETs with a Graded Recess Structure" by Higashisaka et al.
Wong et al, "A Self-Aligned Double Recessed, Sub-Half Micron Gate Process For MMIC's Using DUV Or E-Beam Lithography", Proceedings of . . . The Electrochemical Society, vol. 91-1, 1991, pp. 78-89.
Macksey, "Optimization Of The n.sup.+ Ledge Channel Structure For GaAs Power FET's", IEEE Transactions on Electron Devices, vol. ED-33, No. 11, 1986, pp. 1818-1824.
Tiwari et al., "Physical and Materials Limications on Burnout Voltage of GaAs Powr MESFET's", 8093 IEEE Trans. on Electron Devices, vol. ED-27, No. 6, Jun. 1980.
Loke Steven H.
Mitsubishi Denki & Kabushiki Kaisha
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