Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2010-08-23
2011-11-15
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257SE21546, C257SE21190
Reexamination Certificate
active
08058141
ABSTRACT:
Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
REFERENCES:
patent: 5492858 (1996-02-01), Bose et al.
patent: 5940717 (1999-08-01), Rengarajan et al.
patent: 6245641 (2001-06-01), Shiozawa et al.
patent: 6251746 (2001-06-01), Hong et al.
patent: 6358796 (2002-03-01), Lin et al.
patent: 6461937 (2002-10-01), Kim et al.
patent: 2002/0076900 (2002-06-01), Park et al.
patent: 2002/0109102 (2002-08-01), Steklenski et al.
patent: 2004/0072412 (2004-04-01), Kim
patent: 2005/0173759 (2005-08-01), Kim et al.
patent: 2006/0226455 (2006-10-01), Lee et al.
patent: 1020020061925 (2002-10-01), None
patent: 1020040099533 (2004-12-01), None
USPTO Office Action mailed Dec. 7, 2006 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Jan. 24, 2007 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Jul. 11, 2007 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Nov. 19, 2007 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed May 6, 2008 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Sep. 26, 2008 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Mar. 18, 2009 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Jul. 13, 2009 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Jan. 11, 2010 for U.S. Appl. No. 11/157,999.
USPTO Notice of Allowance mailed May 24, 2010 for U.S. Appl. No. 11/157,999.
USPTO Office Action mailed Jun. 25, 2010 for U.S. Appl. No. 11/157,999.
Jang Se Aug
Kim Jun Ki
Kim Soo Hyun
Sohn Hyun Chul
Fahmy Wael
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Salerno Sarah
LandOfFree
Recessed gate electrode MOS transistor and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Recessed gate electrode MOS transistor and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Recessed gate electrode MOS transistor and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4288331