Reception comparator

Details Reception comparator Reception comparator

1993-09-16

1996-07-23

Tse, Young T.

Pulse or digital communications

Receivers

Automatic baseline or threshold adjustment

375257, 327389, 327434, H04L 2506, H04B 300

Patent

active

055397786

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention relates to a receiving comparator for a data-transmission system.
Receiving comparators for data-transmission systems, in particular for controller-area-network bus systems (CAN bus systems) are generally known. They are used to adapt, or rather to convert, the level of signals which are exchanged between CAN control circuits (CAN controllers) and the CAN bus, to render possible an optimal signal processing. The disadvantage of such known systems is that their space requirements are relatively high, thus resulting in a high manufacturing expenditure and, finally, a high failure quota.


SUMMARY OF THE INVENTION

The receiving comparator in accordance with the present invention has the advantage of requiring very little space. It is also distinguished by a high functional reliability. In addition, any short-circuiting of the CAN-bus lines to ground or to the voltage supply is able to be compensated particularly well. Moreover, the present invention also allows for signals having a high transmission rate to be transmitted. This is achieved by providing the circuit elements of the comparator on a single semiconductor substrate, thereby monolithically integrating the entire circuit arrangement.
A first embodiment of the receiving comparator according to the present invention comprises a signal-conditioning device having a voltage divider, which is provided with a reference-voltage source and whose potential is preferably selected so as to allow the input signals of the following comparator to lie within the supply band. This signal-conditioning device makes it possible to process signals which are being received on the CAN bus and whose potentials lie outside of the supply band of the comparator, thus whose potentials are greater than the positive supply voltage of the comparator and smaller than its negative supply voltage. A short-circuiting of at least one of the data-transmission lines to ground, inclusive of ground offset, or to the supply voltage can thus be compensated.
In addition, a further embodiment of the receiving comparator includes a comparator circuit arrangement, which has a threshold-value generating device, preferably a current source, arranged downstream from the signal-conditioning device. In the case of such a comparator circuit, it is guaranteed that the CAN bus is not brought on to load asymmetrically by the input comparator. This is particularly advantageous when numerous input comparators are linked to the data bus.
Furthermore, one further embodiment of the receiving comparator includes a signal-amplifier stage, which is preferably designed with ECL technology, arranged downstream from the comparator circuit. Such an amplifier stage guarantees a very small signal delay, so that digital signals having a high transmission rate are also able to be transmitted, the input common-mode range extending thereby up to above the supply voltage and to below ground.
Finally, another embodiment of the receiving comparator includes an output stage, preferably comprising MOS-transistors and npn-transistors, arranged downstream from the signal-amplifier stage. Through the selection of such circuit elements, it is guaranteed that this part of the receiving comparator also attains a high switching rate, whereby a large output voltage range is ensured at the same time.
In accordance with a still further embodiment of the present invention, the individual circuit elements are accommodated on one and the same substrate. Synchronous responses to temperature changes are guaranteed thereby, for example, in the case of the resistors of the voltage divider and in the input comparator, so that an optimal temperature compensation is guaranteed.


BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a CAN driver with an input comparator and with a sketched CAN bus.
FIG. 2 shows a basic circuit arrangement of the input comparator that was merely sketched in FIG. 1.


DETAILED DESCRIPTION OF THE DRAWINGS

The input comparator according to the invention can be

REFERENCES:
patent: 4679209 (1987-07-01), Hogeboom et al.
patent: 4847865 (1989-07-01), Larson
patent: 5243625 (1993-09-01), Verbakel et al.
patent: 5321724 (1994-06-01), Long et al.

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