Reception apparatus and method

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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Reexamination Certificate

active

06990160

ABSTRACT:
A phase of a sampling clock provided from clock generating circuit107is switched periodically and alternately with a phase difference of 180 degrees, and during a period of each phase, timing estimating circuit105estimates a symbol timing. High-accuracy timing estimating circuit109selects an estimated result with higher reliability among symbol timing estimated results obtained in respective periods, thereby enabling estimation of the symbol timing with time resolution twice a sampling period. It is possible to decrease an operation frequency in an A/D conversion circuit even in a system requiring timing synchronization accuracy with high accuracy.

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English Language abstract of JP-6-232933.
English Language abstract of JP-55-79541.

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