Receiving counter phase synchronization circuit of the synchrono

Details Receiving counter phase synchronization circuit of the synchrono Receiving counter phase synchronization circuit of the synchrono

1989-12-11

1991-03-26

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

307511, 307526, 375119, H04L 704

Patent

active

050035606

ABSTRACT:
The invention provides a receiving counter phase synchronization circuit of the synchronous transmission system, the circuit comprising first line transmitting the signals of logic status according to whether or not synchronization pattern is detected in the serial bit stream; second line transmitting the pre-existence phase information of the receiving counter; a D flip-flop circuit for outputting the delayed data under the control of a clock signal; first NOR logic device connected to the output line of said D flip-flop circuit and said second line; second NOR logic device connected to said first NOR logic and said first line, and having its output line connected to said the data input node of said D flip-flop circuit; an inverter connected to said first line; and an OR logic device connected to the output line of said inverter and that of said first NOR logic device.

REFERENCES:
patent: 4868512 (1989-09-01), Bridgman

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