Receiving circuitry for receiving serially transmitted encoded i

Details Receiving circuitry for receiving serially transmitted encoded i Receiving circuitry for receiving serially transmitted encoded i

1995-02-07

1998-04-21

Chin, Stephen

Pulse or digital communications

Receivers

370503, 370514, H03K 900, H04L 2706, H04L 2714, H04L 2722

Patent

active

057426449

ABSTRACT:
The present invention provides reconstruction and resynchronization of wireless serial transmissions which are subject to fading causing erroneous uncorrectable bit errors exceeding the error correction code correction capacity present in frames of digitally encoded data. Valid data is reconstructed in frames which are determined to contain at least one erroneous uncorrectable bit exceeding the bit error correction capacity of the error correction code therein which have all erroneous uncorrectable bits within the error correction code bit held. A synchronization marker is transmitted with each frame group which does not represent any valid data in a frame. Detection of the synchronization marker by a digital signal processor after at least one frame is determined to contain at least one erroneous uncorrectable bit, which is indicative of a loss of synchronism of the receiving circuitry clock, resynchronizes the clock of a processor of the receiving circuitry. After resynchronization of the clock, frames beginning with the at least one frame containing the at least one erroneous uncorrectable bit indicative of the loss of clock synchronism to the frames in the frame group containing the synchronization marker are reconstructed to recover a data in frames which do not contain at least one erroneous uncorrectable bit and, as described above, to recover valid data bits in frames containing at least one erroneous uncorrectable bit. Finally, frames transmitted after the detected synchronization marker are processed synchronously including reconstruction or resynchronization as described above.

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